https://github.com/UVVM/UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
https://github.com/UVVM/UVVM

Last synced: about 2 months ago
JSON representation

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

• Host: GitHub
• URL: https://github.com/UVVM/UVVM
• Owner: UVVM
• License: apache-2.0
• Created: 2016-01-21T08:33:04.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2024-08-17T12:15:00.000Z (4 months ago)
• Last Synced: 2024-08-17T13:30:03.985Z (4 months ago)
• Language: VHDL
• Homepage: https://uvvm.github.io/
• Size: 639 MB
• Stars: 352
• Watchers: 54
• Forks: 91
• Open Issues: 24
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGES.TXT
  • License: LICENSE

Awesome Lists containing this project

• awesome-opensource-hardware - uvvm
• awesome-open-hardware-verification - a bunch of stuff