https://github.com/ZipCPU/wbuart32

A simple, basic, formally verified UART controller
https://github.com/ZipCPU/wbuart32

fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus

Last synced: about 1 month ago
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A simple, basic, formally verified UART controller

• Host: GitHub
• URL: https://github.com/ZipCPU/wbuart32
• Owner: ZipCPU
• License: gpl-3.0
• Created: 2016-09-21T14:39:21.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2024-01-29T18:12:25.000Z (7 months ago)
• Last Synced: 2024-06-15T23:35:32.953Z (3 months ago)
• Topics: fpga, serialport, uart, uart-verilog, verilator, verilog, wishbone, wishbone-bus
• Language: Verilog
• Homepage:
• Size: 1.19 MB
• Stars: 261
• Watchers: 15
• Forks: 48
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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