https://github.com/abdelazeem201/leon2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
https://github.com/abdelazeem201/leon2
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Last synced: 3 months ago
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The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
- Host: GitHub
- URL: https://github.com/abdelazeem201/leon2
- Owner: abdelazeem201
- License: mit
- Created: 2023-04-27T11:33:29.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-05-06T15:33:38.000Z (over 2 years ago)
- Last Synced: 2025-04-08T11:06:26.151Z (6 months ago)
- Topics: arm, asic, asic-design, asic-verification, fpga, rtl, simulation, soc, systemverilog, verilog, vhdl
- Language: VHDL
- Homepage: https://www.esa.int/Enabling_Support/Space_Engineering_Technology/Onboard_Computers_and_Data_Handling/Microprocessors
- Size: 816 KB
- Stars: 7
- Watchers: 1
- Forks: 0
- Open Issues: 0