https://github.com/abdelazeem201/leon2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
https://github.com/abdelazeem201/leon2
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Last synced: 4 months ago
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The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
- Host: GitHub
- URL: https://github.com/abdelazeem201/leon2
- Owner: abdelazeem201
- License: mit
- Created: 2023-04-27T11:33:29.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2023-05-06T15:33:38.000Z (about 3 years ago)
- Last Synced: 2025-07-19T08:06:51.145Z (11 months ago)
- Topics: arm, asic, asic-design, asic-verification, fpga, rtl, simulation, soc, systemverilog, verilog, vhdl
- Language: VHDL
- Homepage: https://www.esa.int/Enabling_Support/Space_Engineering_Technology/Onboard_Computers_and_Data_Handling/Microprocessors
- Size: 816 KB
- Stars: 8
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# LEON2 / LEON2-FT
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture. It is highly configurable, and was designed for embedded applications with the following features on-chip:
* 5-stage integer pipeline
* separate instruction and data caches
* hardware multiplier and divider
* memory management unit
* interrupt controller
* debug support unit with trace buffer
* two 24-bit timers
* two UARTs
* power-down function
* watchdog
* 16-bit I/O port
* Flexible memory controller
The LEON2 is based on an AMBA AHB/APB bus architecture, so new modules can easily be added to extend its functionality. The processor can be implemented in both FPGA and ASIC technologies.
The LEON2-FT design is an extension of the basic LEON2 model including advanced fault-tolerance features to withstand arbitrary single-event upset (SEU) errors without loss of data. The fault-tolerance is provided at design (VHDL) level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools. Atmel has manufactured an ASIC version of the LEON2-FT in the ATH18RHA rad hard process, available through their catalogue as part number AT697F. The AT697F is qualified according to QML-Q.
*Availability:*
The LEON2-FT VHDL IP core is available from ESA directly, under special licensing conditions. Please refer to the LEON2-FT IP Core webpage on the ESA IP Cores website for more information on licensing the LEON2-FT model.
The LEON2 (non-FT) model is no longer maintained. It is superceded by LEON2-FT, and the subsequently released LEON models (LEON3, LEON4).
The ASIC implementation of the LEON2-FT is available from Atmel,as part number AT697F.
