https://github.com/abdelazeem201/orca
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
https://github.com/abdelazeem201/orca
asic asic-design fpga-soc hdl pnr rtl saed32nm synopsys synopsys-dc synopsys-iccii synopsys-vcs synthesis systemonchip upf verilog vhdl
Last synced: 4 months ago
JSON representation
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
- Host: GitHub
- URL: https://github.com/abdelazeem201/orca
- Owner: abdelazeem201
- License: mit
- Created: 2023-05-12T22:59:22.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2023-09-10T11:49:52.000Z (over 2 years ago)
- Last Synced: 2023-09-10T12:31:53.486Z (over 2 years ago)
- Topics: asic, asic-design, fpga-soc, hdl, pnr, rtl, saed32nm, synopsys, synopsys-dc, synopsys-iccii, synopsys-vcs, synthesis, systemonchip, upf, verilog, vhdl
- Language: Verilog
- Homepage:
- Size: 86.6 MB
- Stars: 3
- Watchers: 2
- Forks: 1
- Open Issues: 0