https://github.com/aletempiac/dlx
Digital design and synthesis of a DLX processor in VHDL
https://github.com/aletempiac/dlx
alu dlx dlx-processor processor vhdl
Last synced: about 2 months ago
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Digital design and synthesis of a DLX processor in VHDL
- Host: GitHub
- URL: https://github.com/aletempiac/dlx
- Owner: aletempiac
- License: gpl-3.0
- Created: 2018-10-14T15:54:40.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2019-03-17T10:47:10.000Z (about 6 years ago)
- Last Synced: 2025-02-03T18:01:36.875Z (4 months ago)
- Topics: alu, dlx, dlx-processor, processor, vhdl
- Language: VHDL
- Homepage:
- Size: 14.4 MB
- Stars: 1
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# DLX processor project
The project contains all the VHDL code of a processor, see the [report] for further details.
## How to simulate
In order to simulate the design, you have to compile your DLX assembly, you have a complete list of all the instructions in the [report]. The compiler is called by [assembler.sh] on a file containing the assembly.
For instance in the command line:
```bash
$ ./assembler.sh BranchPrediction.asm.txt
```
It will generate the machine code that will be read by the Instruction Memory at the start of the simulation.
Use the script [DLX_sim.scr] to compile the design in ModelSim using
```bash
$ source DLX_sim.scr
```
## Synthesis
The design present in the `Synthesis` folder is fully synthesizable and [DLX.scr] compiles for Synopsys Design Compiler.
### Developers: Alessandro Tempia Calvino, Fausto Chiatante
Possible improvements in background:
- Add floating-point units to the design
- Multi-cycle execution
[report]: Report.pdf
[assembler.sh]: Simulation/assembler.sh
[DLX_sim.scr]: Simulation/DLX_sim.scr
[DLX.scr]: Synthesis/DLX.scr