https://github.com/aliiimaher/mips-verilog

MIPS architecture implemented in Verilog.
https://github.com/aliiimaher/mips-verilog

mips mips-architecture pipeline-mips verilog

Last synced: about 1 month ago
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MIPS architecture implemented in Verilog.

• Host: GitHub
• URL: https://github.com/aliiimaher/mips-verilog
• Owner: aliiimaher
• License: mit
• Created: 2023-01-30T18:48:24.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-01-30T20:05:49.000Z (about 2 years ago)
• Last Synced: 2024-11-13T20:41:53.591Z (3 months ago)
• Topics: mips, mips-architecture, pipeline-mips, verilog
• Language: C
• Homepage:
• Size: 1.64 MB
• Stars: 9
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# MIPS-Verilog

MIPS architecture implemented in Verilog.

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## A 5-stage Pipelined MISP32 Processor

Five stages of a microprocessor: 

- Instruction Fetch (IF)

- Instruction Decode (ID)

- Execution(EX) 

- Memory Access and Write (MEM) 

- Write Back (WB)

![MIPS](https://user-images.githubusercontent.com/93030419/215577717-bc5c4d0b-d224-41eb-86b9-c2acf24af725.jpg)

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### Instructions supported:

1. R-type Instructions (ADD, SUB, AND, OR, SLT, LSL, LSR, NOT)

2. LW and SW

3. ADDI

4. BEQ

5. SLTI

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### Supplementary Details:

This is MIPS 32 bits architecture with a 5-stage design to implement in 6 homework. And this is for the "Computer Architecture Lab" course at Shiraz university in Fall 2022.

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### How to run project?

Clone the GitHub repository and open the project folder in Xillinix to run the simulation. Note that this implementation reads the instructions from a file.