https://github.com/aliiiw/computer-architecture-lab
Implement Mips cpu with Verilog
https://github.com/aliiiw/computer-architecture-lab
forwarding mips pipeline verilog
Last synced: 4 months ago
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Implement Mips cpu with Verilog
- Host: GitHub
- URL: https://github.com/aliiiw/computer-architecture-lab
- Owner: Aliiiw
- Created: 2022-11-04T07:55:15.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2023-01-22T10:34:48.000Z (over 3 years ago)
- Last Synced: 2025-10-26T05:40:30.814Z (8 months ago)
- Topics: forwarding, mips, pipeline, verilog
- Language: Verilog
- Homepage:
- Size: 871 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Computer-Architecture-Lab
Implement Mips cpu with Verilog