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https://github.com/alirezakay/risc-cpu

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
https://github.com/alirezakay/risc-cpu

cpu cpu-architecture cpu-model instruction-set-architecture isa mips-processor multi-cycle processor-architecture processor-design risc-processor vhdl vhdl-code vhdl-modules

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A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

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# RISC-CPU
> A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

## Documentation
This project is implemented in `VHDL` language with `ISE` simulator software with **a particular specifications**.

Relevant course for this project could be `computer architecture`.

These codes here in github, are just the vhdl and wave files.

If you wanna get the ***complete project codes, built with `ISE`*** go [here](https://alirezakay.github.io/showcase/y2/risc-cpu-simulation), find the project title and **download** the full one.

here is a fairly complete documentaion written in **Persian** and also **English** languages: [document](./MyCPU.pdf)


![image 1 - cpu](https://alirezakay.github.io/showcase/y2/img/CPU2.png)

![image 2 - cpu](https://alirezakay.github.io/showcase/y2/img/CPU3.png)


## Authors

[Alireza Kavian](https://alireza-kavian.github.io)

## License

This project is licensed under the MIT License - see the [LICENSE](./LICENSE) file for details