https://github.com/antonioberna/vlsi

Very Large Scale Integration (VLSI) Design
https://github.com/antonioberna/vlsi

asm assembly c digital-electronics fsm pic rtl surfer verilog vhdl

Last synced: about 1 month ago
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Very Large Scale Integration (VLSI) Design

• Host: GitHub
• URL: https://github.com/antonioberna/vlsi
• Owner: AntonioBerna
• License: gpl-3.0
• Created: 2026-03-13T12:42:22.000Z (4 months ago)
• Default Branch: master
• Last Pushed: 2026-03-13T16:24:27.000Z (4 months ago)
• Last Synced: 2026-03-14T01:31:09.781Z (4 months ago)
• Topics: asm, assembly, c, digital-electronics, fsm, pic, rtl, surfer, verilog, vhdl
• Language: VHDL
• Homepage:
• Size: 4.53 MB
• Stars: 0
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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    Very Large Scale Integration (VLSI) Design

    




> [!WARNING]

> This repository is unfinished. Keep your expectations low.

## Requirements

- [GHDL](https://github.com/ghdl/ghdl) for VHDL simulation.

- [Icarus Verilog](https://github.com/steveicarus/iverilog) for Verilog simulation.

- [Surfer](https://github.com/samitbasu/surfer-project-rhdl) for waveform visualization.

- [VHDL Style Guide](https://github.com/jeremiah-c-leary/vhdl-style-guide) for VHDL linting and formatting.

- [Verible](https://github.com/chipsalliance/verible) for Verilog linting and formatting.