https://github.com/anuejn/xc9500
WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
https://github.com/anuejn/xc9500
cpld digital-logic reverse-engineering yosys
Last synced: 12 months ago
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WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
- Host: GitHub
- URL: https://github.com/anuejn/xc9500
- Owner: anuejn
- Created: 2019-01-26T21:21:16.000Z (about 7 years ago)
- Default Branch: master
- Last Pushed: 2021-11-05T22:32:01.000Z (over 4 years ago)
- Last Synced: 2025-03-27T11:43:36.413Z (12 months ago)
- Topics: cpld, digital-logic, reverse-engineering, yosys
- Language: Python
- Size: 1.6 MB
- Stars: 10
- Watchers: 3
- Forks: 3
- Open Issues: 1
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Metadata Files:
- Readme: README.md
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README
# XC9500 Reverse Engineering
WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
Primary focus of efford is on the XC9572XL for now.
## Useful documentation
To get started the following documents are a good intro into the architecture:
* [The Family Datasheet](https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf)
* [The xc3sprog code and documentation](https://sourceforge.net/projects/xc3sprog/) (or see submodule in `bitstream/xc3sprog`)
## Bitstream Documentation
Some initial thoughts have been made on which bits / fuses exist, but they still have to be located in the bitstream.
For example bitstreams, see the `misc/bitstreams/` folder.
## Simulator
Nothing is done on this front yet.
A complete model of the CPLD is to be written. It should be able to be "programmed" with real bitstreams in jedec format and should behave like a real cpld.
## Yosys Backend
Nothing is done on this front yet.
The primary goal is to be able to go from yosys rtlil to a working bitstream in jedec file format.
Timing optimization / analysis is only secondary for now.