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https://github.com/anuragnatoo/ele301p
VLSI System Design Practice Lab
https://github.com/anuragnatoo/ele301p
activity-factors practice-lab python python-application test-bench verilog vlsi
Last synced: 12 days ago
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VLSI System Design Practice Lab
- Host: GitHub
- URL: https://github.com/anuragnatoo/ele301p
- Owner: anuragnatoo
- License: mit
- Created: 2019-08-06T17:14:09.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-04-21T05:15:53.000Z (almost 5 years ago)
- Last Synced: 2024-11-12T20:11:26.063Z (2 months ago)
- Topics: activity-factors, practice-lab, python, python-application, test-bench, verilog, vlsi
- Language: Verilog
- Size: 36.1 KB
- Stars: 1
- Watchers: 1
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# ELE301P
VLSI System Design Practice Lab## Contents
* Verilog
* Adders:
* Ripple Carry Adders: 4 bit,8 bit,16 bit,32 bit and 64 bit Ripple Carry Adder implemented in Verilog HDL
* Carry Save Adder: A 16 bit Recursive Doubling Adder implemented in Verilog HDL
* Python
* Test Bench Generator: A python application which generates a test bench of a given verilog file
* To RUN the file : `python3 tbgen.py filename.v`
* The output is stored as `filename_tb.v`
* Make sure that the verilog file is in the same folder as the tbgen.py
* ISCAS Benchmark Verilog files are taken as input
* For convenience the inputs and outputs are placed in different folders. But while compiling they need to be in the same folder.
* Activity Factor Calculator: A python application which calculates the activity factors of the output elements and lists them down in a text file
* To RUN the file : `python3 da2.py filename.v`
* The output is stored as `filename.txt`
* Make sure that the verilog and the python files are in the same folder
* ISCAS Benchmark Verilog files are taken as inputs
* For convenience the inputs and outputs are placed in different folders. But while compiling they need to be in the same folder.