https://github.com/anushangapavith/building-a-simple-processor-memory-hierarchy

Group mini project (Lab 05, 06) in Computer Architecture Course
https://github.com/anushangapavith/building-a-simple-processor-memory-hierarchy

Last synced: about 1 month ago
JSON representation

Group mini project (Lab 05, 06) in Computer Architecture Course

• Host: GitHub
• URL: https://github.com/anushangapavith/building-a-simple-processor-memory-hierarchy
• Owner: AnushangaPavith
• Created: 2022-06-22T09:32:56.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2022-06-30T11:40:07.000Z (over 2 years ago)
• Last Synced: 2023-03-06T02:54:08.784Z (almost 2 years ago)
• Language: Verilog
• Size: 9.57 MB
• Stars: 5
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# Building-a-simple-processor-Memory-hierarchy

Group mini project (Lab 05, 06) in Computer Architecture Course

## Pre requests

verilog compiler(Icarus Verilog) with GTKWave.

## Compile & run the verilog file

`iverilog -o fileName fileName.v`

Then it will create a binary file

`vvp fileName`

This will run the binary file and give outputs

## Run the GTKwaveData (if avalable)

`gtkwave GTKwaveFileName.vcd`

The GTKWave will open automatically

Then you can select components that want to show from the left tab

Instruction file "instr_mem.mem" will be needed to run the CPU properly.

It should be in the same directory with verilog file. If not, change the path in verilog file.