https://github.com/apertus-open-source-cinema/naps

An experiment for building gateware for the axiom micro / beta using amaranth-hdl
https://github.com/apertus-open-source-cinema/naps

axiom-beta compression fpga gateware hacktoberfest machxo nmigen python soc video wavelet zynq

Last synced: 3 days ago
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An experiment for building gateware for the axiom micro / beta using amaranth-hdl

• Host: GitHub
• URL: https://github.com/apertus-open-source-cinema/naps
• Owner: apertus-open-source-cinema
• License: gpl-3.0
• Created: 2019-03-22T20:50:55.000Z (almost 6 years ago)
• Default Branch: main
• Last Pushed: 2024-04-29T13:55:14.000Z (8 months ago)
• Last Synced: 2024-10-04T09:24:44.903Z (3 months ago)
• Topics: axiom-beta, compression, fpga, gateware, hacktoberfest, machxo, nmigen, python, soc, video, wavelet, zynq
• Language: Python
• Homepage: https://apertus-open-source-cinema.github.io/naps/intro.html
• Size: 42.5 MB
• Stars: 37
• Watchers: 11
• Forks: 4
• Open Issues: 4
• Metadata Files:
  • Readme: README.rst
  • License: LICENSE

Awesome Lists containing this project

• amaranth-awesome - naps

README

        
naps - The Relaxed Amaranth Packages Collection

=======================================================

Building Blocks & Tools for FPGA Design with Python & `Amaranth HDL `__.

Mostly a place to experiment and figure out how to build things.

Also the incubator for the future AXIOM Beta camera gateware & the home of the current AXIOM micro gateware.

This repo contains:

-  Prototypes of the upcoming Amaranth data types ``PackedStruct`` and ``Interface`` (here called ``Bundle``) (in ``src/lib/data_structure/``)

-  A stream Abstraction with various building Blocks: (in ``src/lib/stream/``)

   -  FIFOs

   -  A gearbox for changing the width

   -  Helpers for building other Stream cores

   -  Miscellaneous Debug and Inspection tools

-  various Amaranth cores (in ``src/lib/``) for:

   -  AXI and AXI Lite including a Buffer reader and Writer

   -  A CSR bank that can be wired to an AXI bus

   -  HDMI (currently the DVI subset; derived from Litevideo)

   -  A HISPI reciever (for the use with aptina / onsemi image sensors)

   -  A core for streaming data over USB3 using the ft601

   -  Some utility video processing (like debayering)

   -  …

-  tools for gluing together SOCs (currently supports the Xilinx Zynq and JTAG based plattoforms) in ``src/soc/``

   -  Making heavy use of Amaranth HDL Platform abstractions (wrapping existing plattforms)

   -  Provides a bus agnostic way to describe (low speed) peripherals

   -  Emits Python code that can be used to access the designs CSRs (“pydriver”)

   -  Generate devicetree overlays for loading linux device drivers

   -  pack “fatbitstreams” that bundle setup logic, drivers and the bitstream

   -  there is a `Poster about the naps soc infrastructure `__.

-  platform definitions for both the AXIOM Beta and the AXIOM Micro in ``src/devices/``

-  a variety of other smaller half-working experiments in ``src/experiments/``

   -  linux framebuffer HDMI output

   -  USB3 Plugin module gateware (wip)

   -  AXIOM micro camera gateware (wip)

   -  test gateware to test connectors for their ability to transmit high speed data (via a loopback test)

   -  test gateware for the axi writer & reader

Installation

------------

Installing