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amaranth-awesome
Awesome projects using the Amaranth HDL
https://github.com/robtaylor/amaranth-awesome
Last synced: 2 days ago
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- amaranth-soc - on-a-Chip Framework.
- amaranth-stdio
- RFCs
- template-fpga
- Minerva - V](https://riscv.org/specifications/) RV32IMZicsr instruction set built by the maintainer of Amaranth SoC.
- amaranth-soc - on-a-Chip Framework.
- amaranth-stdio
- ORBTrace - HS Debug and Trace interface for ARM CORTEX-M processors.
- mtkCPU
- niar
- pytest-amaranth-sim
- sae
- smolarith - cores for smol FPGAs.
- amaranth-examples
- EMBR RV32
- hapenny - width RISC-V CPU implementation designed to evaluate the Amaranth HDL, operating internally on 16-bit chunks while executing the RV32I instruction set.
- ROOM - stage out-of-order RV64IMFDC CPU
- Manta
- naps
- Niar
- patina - V FPGA control plane development.
- maia-sdr - source FPGA-based SDR project focusing on the ADALM Pluto. It uses Amaranth-HDL for many DSP Blocks.
- Cynthion - in-one tool for building, testing, and experimenting with USB devices using a customizable FPGA-based architecture.
- Apertus
- Coreblocks - of-order [RISC-V](https://riscv.org/specifications/) core generator implemented in Amaranth.
- Glasgow
- LUNA
- Lambdalib
- ORBTrace - HS Debug and Trace interface for ARM CORTEX-M processors.
- Tiliqua - based audio multitool for Eurorack.
- amaranth-exercises
- amaranth-lib-bl0x - HDL.
- amaranth-orchard
- amaranth-stubs
- hexastorm
- ili9341spi
- learn-fpga-amaranth - fpga tutorial by Bruno Levy from blinker to RISC-V using Amaranth HDL
- Minerva - V](https://riscv.org/specifications/) RV32IMZicsr instruction set built by the maintainer of Amaranth SoC.
- Coreblocks - of-order [RISC-V](https://riscv.org/specifications/) core generator implemented in Amaranth.
- Glasgow
- LUNA
- Lambdalib
- Tiliqua - based audio multitool for Eurorack.
- amaranth-exercises
- amaranth-lib-bl0x - HDL.
- amaranth-stubs
- hexastorm
- ili9341spi
- learn-fpga-amaranth - fpga tutorial by Bruno Levy from blinker to RISC-V using Amaranth HDL
- mtkCPU
- niar
- pytest-amaranth-sim
- sae
- sentinel - V CPU (RV32I_Zicsr) written in Amaranth. It implements the Machine Mode privileged spec, and is designed to fit into ~1000 4-input LUTs or less on an FPGA.
- smolarith - cores for smol FPGAs.
- LambdaConcept - demand software development and hardware programming for a wide range of embedded systems.
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Categories
Sub Categories
Keywords
fpga
18
amaranth-hdl
9
amaranth
7
riscv
6
python
4
nmigen
3
system-on-chip
2
interface
2
cpu
2
gdb
2
mmu
2
openocd
2
openocd-riscv
2
zig
2
raspberry
2
micropython
2
laser-scanner
2
laser
2
cnc-machine
2
usb
2
hardware
2
risc-v
2
webgl2
1
wasm
1
signal-processing
1
sdr
1
debug
1
icestick
1
icestorm
1
verilog
1
xilinx
1
axiom-beta
1
compression
1
gateware
1
machxo
1
soc
1
video
1
wavelet
1
zynq
1
adalm-pluto
1
dsp
1
radio
1
rust
1