https://github.com/fischermoseley/manta

A configurable and approachable tool for FPGA debugging and rapid prototyping.
https://github.com/fischermoseley/manta

debug fpga icestick icestorm verilog xilinx

Last synced: 2 months ago
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A configurable and approachable tool for FPGA debugging and rapid prototyping.

• Host: GitHub
• URL: https://github.com/fischermoseley/manta
• Owner: fischermoseley
• License: gpl-3.0
• Created: 2023-02-04T15:00:25.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2026-03-29T03:44:05.000Z (3 months ago)
• Last Synced: 2026-03-29T05:20:04.627Z (3 months ago)
• Topics: debug, fpga, icestick, icestorm, verilog, xilinx
• Language: Python
• Homepage: https://fischermoseley.github.io/manta/
• Size: 10.3 MB
• Stars: 146
• Watchers: 4
• Forks: 13
• Open Issues: 10
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE.txt

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README

          
![](https://raw.githubusercontent.com/fischermoseley/manta/refs/heads/main/doc/assets/logo.png)

## Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping

![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg)

![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg)

[![codecov](https://codecov.io/gh/fischermoseley/manta/graph/badge.svg?token=1GGHCICK3Q)](https://codecov.io/gh/fischermoseley/manta)

[![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0)

[![Ruff](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/astral-sh/ruff/main/assets/badge/v2.json)](https://github.com/astral-sh/ruff)

Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.

For more information check out the docs:

[https://fischermoseley.github.io/manta](https://fischermoseley.github.io/manta)