https://github.com/avakar/better_verilog

https://github.com/avakar/better_verilog

Last synced: 2 days ago
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• Host: GitHub
• URL: https://github.com/avakar/better_verilog
• Owner: avakar
• Created: 2015-12-17T15:30:05.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2016-01-10T21:12:10.000Z (almost 9 years ago)
• Last Synced: 2024-10-08T00:43:45.988Z (about 1 month ago)
• Language: Python
• Size: 24.4 KB
• Stars: 2
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
[![Build Status](https://travis-ci.org/avakar/better_verilog.svg?branch=master)](https://travis-ci.org/avakar/better_verilog)

A succint, yet expressive HDL.

Getting started

===============

Install the project using pip:

    $ pip install better_verilog

Open your favorite editor and create a new file called hello_world.bv.

Type the following.

    module hello:

        i clk

        o led

    def hello:

        on posedge clk:

            led <= not led

Run the translator:

    $ bv hello_world.bv > hello_world.v

    $ cat hello_world.v

    module hello(

        input clk,

        output reg led

        );

    always @(posedge clk) begin

        led <= !led;

    end

    endmodule

Synthetize or simulate hello_world.v.