https://github.com/ben-marshall/uart

A simple implementation of a UART modem in Verilog.
https://github.com/ben-marshall/uart

fpga hardware uart uart-verilog verilog verilog-hdl

Last synced: about 1 month ago
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A simple implementation of a UART modem in Verilog.

• Host: GitHub
• URL: https://github.com/ben-marshall/uart
• Owner: ben-marshall
• License: mit
• Created: 2017-02-04T14:11:49.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2021-11-10T14:53:07.000Z (about 3 years ago)
• Last Synced: 2023-03-02T02:05:43.340Z (almost 2 years ago)
• Topics: fpga, hardware, uart, uart-verilog, verilog, verilog-hdl
• Language: Verilog
• Homepage: https://ben-marshall.github.io/uart/
• Size: 53.7 KB
• Stars: 48
• Watchers: 3
• Forks: 17
• Open Issues: 1

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