https://github.com/ben-marshall/uart
A simple implementation of a UART modem in Verilog.
https://github.com/ben-marshall/uart
fpga hardware uart uart-verilog verilog verilog-hdl
Last synced: 4 months ago
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A simple implementation of a UART modem in Verilog.
- Host: GitHub
- URL: https://github.com/ben-marshall/uart
- Owner: ben-marshall
- License: mit
- Created: 2017-02-04T14:11:49.000Z (about 9 years ago)
- Default Branch: master
- Last Pushed: 2021-11-10T14:53:07.000Z (over 4 years ago)
- Last Synced: 2025-02-03T17:49:14.232Z (about 1 year ago)
- Topics: fpga, hardware, uart, uart-verilog, verilog, verilog-hdl
- Language: Verilog
- Homepage: https://ben-marshall.github.io/uart/
- Size: 53.7 KB
- Stars: 117
- Watchers: 4
- Forks: 23
- Open Issues: 3