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https://github.com/ben-marshall/verilog-probe
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
https://github.com/ben-marshall/verilog-probe
debugger fpga hdl probe python3 uart verilog
Last synced: about 2 months ago
JSON representation
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
- Host: GitHub
- URL: https://github.com/ben-marshall/verilog-probe
- Owner: ben-marshall
- License: mit
- Created: 2017-08-15T20:34:15.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2017-09-12T19:10:35.000Z (over 7 years ago)
- Last Synced: 2023-03-02T02:05:43.542Z (almost 2 years ago)
- Topics: debugger, fpga, hdl, probe, python3, uart, verilog
- Language: Python
- Size: 203 KB
- Stars: 6
- Watchers: 2
- Forks: 2
- Open Issues: 1