https://github.com/ben-marshall/verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
https://github.com/ben-marshall/verilog-probe

debugger fpga hdl probe python3 uart verilog

Last synced: 4 months ago
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A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

• Host: GitHub
• URL: https://github.com/ben-marshall/verilog-probe
• Owner: ben-marshall
• License: mit
• Created: 2017-08-15T20:34:15.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2017-09-12T19:10:35.000Z (almost 9 years ago)
• Last Synced: 2025-04-22T19:11:28.265Z (about 1 year ago)
• Topics: debugger, fpga, hdl, probe, python3, uart, verilog
• Language: Python
• Size: 203 KB
• Stars: 11
• Watchers: 2
• Forks: 3
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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README

          

# Verilog Probe

[![Documentation Status](https://readthedocs.org/projects/verilog-probe/badge/?version=latest)](http://verilog-probe.readthedocs.io/README)

A simple probe which takes commands & data over a simple interface and allows

software based control of an AXI bus and some general purpose registers.

---

## Implementation Details

All implementation stats are taken from the default Xilinx Vivado 2016.4

build flow, targeting an Artix-7 FPGA at speed grade `-3`.

Stat                       | Value

---------------------------|---------------------------------------------

 Flip-Flops                | 87  

 Latches                   | 0

 LUTs                      | 187

 Timing slack @ 100MHz     | 3.77ns

![Cell Map](cells.png)