https://github.com/bharadwaj-r/basic-verilog-codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.
https://github.com/bharadwaj-r/basic-verilog-codes

adder asynchronous comparator decoder demux encoder flipflop gates mux register shift synchronous testbench verilog verilog-vhdl

Last synced: 2 months ago
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Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

• Host: GitHub
• URL: https://github.com/bharadwaj-r/basic-verilog-codes
• Owner: Bharadwaj-R
• License: mit
• Created: 2025-03-31T16:19:53.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2025-03-31T16:28:04.000Z (about 1 year ago)
• Last Synced: 2025-09-17T20:33:52.740Z (7 months ago)
• Topics: adder, asynchronous, comparator, decoder, demux, encoder, flipflop, gates, mux, register, shift, synchronous, testbench, verilog, verilog-vhdl
• Language: Verilog
• Homepage:
• Size: 21.5 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# Basic Verilog Codes

Compiled set of verilog codes for beginners. Can help you with getting started with the basics of verilog. Each code has it's own testbench written at the end of the code file in comments, and some files even have different styles of writing the code. Comment and un-comment the required part of the code as needed.