https://github.com/blark/6502_verilog_src

Fun with a 6502 and an FPGA.
https://github.com/blark/6502_verilog_src

Last synced: 5 months ago
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Fun with a 6502 and an FPGA.

• Host: GitHub
• URL: https://github.com/blark/6502_verilog_src
• Owner: blark
• Created: 2013-11-04T20:47:35.000Z (over 12 years ago)
• Default Branch: master
• Last Pushed: 2013-11-08T01:57:16.000Z (over 12 years ago)
• Last Synced: 2025-05-21T17:13:55.940Z (about 1 year ago)
• Language: Verilog
• Homepage:
• Size: 145 KB
• Stars: 3
• Watchers: 2
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README

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README

          
6502 fpga/cpld interface fun

============================

Experimental stuff for using the Mojo FPGA dev board with a WDC 65C02 MPU. 

The plan, using logic to do:

- WORKING: 1Mhz clock with enable switch (and single step button) 

- Bus decoding to select the right chip

- Other bus stuff:

    - use Mojo - AVR serial to send address bus to PC to see what's on it

    - interface 6502 with SPI SRAM 

- FPGA can be used as ROM to get the party started

... probably more. 

To get in touch with me email: 

blark -at- pwnp -dot- al

Twitter @markbaseggio