https://github.com/brakmic/blinker2

A simple Hardware Design for Xilinx Spartan-6 FPGA written in VHDL
https://github.com/brakmic/blinker2

fpga vhdl

Last synced: 3 days ago
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A simple Hardware Design for Xilinx Spartan-6 FPGA written in VHDL

• Host: GitHub
• URL: https://github.com/brakmic/blinker2
• Owner: brakmic
• License: mit
• Created: 2016-04-03T20:48:21.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2016-04-04T20:49:58.000Z (almost 9 years ago)
• Last Synced: 2024-12-24T06:13:46.725Z (12 days ago)
• Topics: fpga, vhdl
• Language: VHDL
• Size: 142 KB
• Stars: 3
• Watchers: 3
• Forks: 0
• Open Issues: 0

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