https://github.com/carlosedp/chisel-template

Chisel HDL Template Repository
https://github.com/carlosedp/chisel-template

chisel fpga hardware hdl scala

Last synced: 11 months ago
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Chisel HDL Template Repository

• Host: GitHub
• URL: https://github.com/carlosedp/chisel-template
• Owner: carlosedp
• License: bsd-3-clause
• Created: 2021-06-25T21:15:11.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2023-02-11T17:18:55.000Z (almost 3 years ago)
• Last Synced: 2025-03-17T08:21:23.419Z (11 months ago)
• Topics: chisel, fpga, hardware, hdl, scala
• Language: Scala
• Homepage:
• Size: 52.7 KB
• Stars: 7
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: Readme.md
  • License: LICENSE

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README

          
# Chisel Template

[![Scala CI](https://github.com/carlosedp/chisel-template/actions/workflows/scala.yml/badge.svg)](https://github.com/carlosedp/chisel-template/actions/workflows/scala.yml)

This is template project to demonstrate [Chisel](https://www.chisel-lang.org/) functionality with build scripts and tooling. The build is handled by Scala [mill](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html) with some make targets for ease-of-use.

The project includes a simple module (to be replaced with your design) and also have a test spec written with the [scalatest](https://www.scalatest.org/) and [chiseltest](https://github.com/ucb-bar/chiseltest) frameworks. The repository also have a GitHub Action to run automated tests on main branch and PRs.

Chisel Learning Resources:

- [Chisel Book](https://github.com/schoeberl/chisel-book)

- [Chisel Documentation](https://www.chisel-lang.org/chisel3/)

- [Chisel API](https://www.chisel-lang.org/api/latest/chisel3/index.html)

Software requirements:

- Java JDK () - Mandatory

- Gnu Make to run the generation targets

- Verilator (as an option for simulation) - Optional

- GTKWave (to visualize VCD files) - Optional

## Generating Verilog

Verilog code can be generated from Chisel by using the `chisel` Makefile target.

```sh

make chisel

```

The output verilog files are generated in the `./generated` directory.

Running tests can be done with:

```sh

make test

```

More targets can be listed by running `make`.