https://github.com/catkira/dds

HDL code for a DDS (direct digital synthesizer) with AXI stream interface
https://github.com/catkira/dds

dds fpga hdl verilog

Last synced: 3 months ago
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HDL code for a DDS (direct digital synthesizer) with AXI stream interface

• Host: GitHub
• URL: https://github.com/catkira/dds
• Owner: catkira
• License: gpl-3.0
• Created: 2021-02-16T10:39:23.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2022-12-26T10:22:12.000Z (about 2 years ago)
• Last Synced: 2023-03-03T09:54:05.234Z (almost 2 years ago)
• Topics: dds, fpga, hdl, verilog
• Language: Python
• Homepage:
• Size: 65.4 KB
• Stars: 6
• Watchers: 2
• Forks: 0
• Open Issues: 0

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