https://github.com/catkira/dds
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
https://github.com/catkira/dds
dds fpga hdl verilog
Last synced: 7 months ago
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HDL code for a DDS (direct digital synthesizer) with AXI stream interface
- Host: GitHub
- URL: https://github.com/catkira/dds
- Owner: catkira
- License: gpl-3.0
- Created: 2021-02-16T10:39:23.000Z (about 5 years ago)
- Default Branch: master
- Last Pushed: 2023-04-16T20:52:59.000Z (almost 3 years ago)
- Last Synced: 2025-03-29T20:43:55.766Z (11 months ago)
- Topics: dds, fpga, hdl, verilog
- Language: Python
- Homepage:
- Size: 54.7 KB
- Stars: 18
- Watchers: 2
- Forks: 3
- Open Issues: 1