https://github.com/chipsalliance/f4pga-examples
Example designs showing different ways to use F4PGA toolchains.
https://github.com/chipsalliance/f4pga-examples
conda-packages f4pga fpga fpga-designs litex symbiflow-toolchains verilog vexriscv
Last synced: 12 days ago
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Example designs showing different ways to use F4PGA toolchains.
- Host: GitHub
- URL: https://github.com/chipsalliance/f4pga-examples
- Owner: chipsalliance
- License: apache-2.0
- Created: 2020-04-20T14:26:30.000Z (about 5 years ago)
- Default Branch: main
- Last Pushed: 2024-03-27T11:22:53.000Z (about 1 year ago)
- Last Synced: 2025-04-10T00:39:02.136Z (12 days ago)
- Topics: conda-packages, f4pga, fpga, fpga-designs, litex, symbiflow-toolchains, verilog, vexriscv
- Language: Verilog
- Homepage: https://f4pga-examples.readthedocs.io
- Size: 113 MB
- Stars: 275
- Watchers: 23
- Forks: 78
- Open Issues: 118
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# F4PGA examples
This repository provides example FPGA designs that can be built using the F4PGA open source toolchain.
These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices.* Please refer to the [](https://f4pga-examples.readthedocs.io)
for a proper guide on how to run these examples, as well as instructions on how to build and compile your own HDL designs using
the F4PGA toolchain.
* See [](https://f4pga.readthedocs.io/projects/arch-defs/)
to contribute on the development of architecture support in F4PGA.The repository includes:
* [xc7/](./xc7) and [eos-s3/](./eos-s3) - Examples for Xilinx 7-Series and EOS-S3 devices, including:
* Verilog code
* Pin constraints files
* Timing constraints files
* Makefiles for running the F4PGA toolchain
* [docs/](./docs) - Guide on how to get started with F4PGA and build provided examples
* [.github/](./.github) - Directory with CI configuration and scripts
The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets
with [tuttest](https://github.com/antmicro/tuttest).