https://github.com/chipsalliance/f4pga-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.
https://github.com/chipsalliance/f4pga-sdf-timing

interconnect-delays python-sdf-timing sdf symbiflow verilog

Last synced: 2 months ago
JSON representation

Python library for working Standard Delay Format (SDF) Timing Annotation files.

• Host: GitHub
• URL: https://github.com/chipsalliance/f4pga-sdf-timing
• Owner: chipsalliance
• License: apache-2.0
• Created: 2019-04-04T22:54:54.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2024-07-12T13:01:45.000Z (6 months ago)
• Last Synced: 2024-11-01T02:35:44.829Z (2 months ago)
• Topics: interconnect-delays, python-sdf-timing, sdf, symbiflow, verilog
• Language: Python
• Size: 130 KB
• Stars: 28
• Watchers: 13
• Forks: 16
• Open Issues: 7
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# python-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

# [Standard Delay Format](https://en.wikipedia.org/wiki/Standard_Delay_Format)

From Wikipedia;

> Standard Delay Format (SDF) is an IEEE standard for the representation and

> interpretation of timing data for use at any stage of an electronic design

> process. It finds wide applicability in design flows, and forms an efficient

> bridge between

> [Dynamic timing verification](https://en.wikipedia.org/wiki/Dynamic_timing_verification) and

> [Static timing analysis](https://en.wikipedia.org/wiki/Dynamic_timing_verification).

>

> ...

>

> It is an ASCII format that is represented in a tool and language independent

> way and includes path delays, timing constraint values, interconnect delays

> and high level technology parameters.

>

> It has usually two sections: one for interconnect delays and the other for

> cell delays.

>

> SDF format can be used for back-annotation as well as forward-annotation.

# Links

 * [python-sdf-timing GitHub Repository](https://github.com/chipsalliance/python-sdf-timing)

 * [SDF Parser written in C++](https://github.com/kmurray/libsdcparse) -

 * [Verilog To Routing](https://docs.verilogtorouting.org/en/latest/tutorials/timing_simulation/#post-imp-sdf) -

   Verilog to Routing can generate an SDF file for doing post implementation timing simulation.