https://github.com/cpldcpu/llm_hdl_design

Some hardware design experiments using large language models
https://github.com/cpldcpu/llm_hdl_design

Last synced: about 1 year ago
JSON representation

Some hardware design experiments using large language models

• Host: GitHub
• URL: https://github.com/cpldcpu/llm_hdl_design
• Owner: cpldcpu
• License: mit
• Created: 2023-05-22T17:34:35.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2025-03-01T16:20:54.000Z (over 1 year ago)
• Last Synced: 2025-03-26T10:05:09.733Z (about 1 year ago)
• Language: Python
• Size: 111 KB
• Stars: 5
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
# LLM_HDL_Design

Some hardware design experiments using large language models

This repo is mostly interesting for its history. I tracked

the ability of LLMs to generate a simple CPU core in Verilog

starting in early 2023. Once Sonnet 3.5 was released in 

June 2024, it was able to one-shot everything so that it

did not make sense to continue and further.