https://github.com/csp02/rv32i

https://github.com/csp02/rv32i

Last synced: 3 months ago
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• Host: GitHub
• URL: https://github.com/csp02/rv32i
• Owner: CSP02
• License: mit
• Created: 2026-02-19T14:06:46.000Z (4 months ago)
• Default Branch: main
• Last Pushed: 2026-03-27T02:35:31.000Z (3 months ago)
• Last Synced: 2026-03-27T15:08:50.565Z (3 months ago)
• Language: Verilog
• Size: 104 KB
• Stars: 0
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# 🧠 RV32I Pipelined Processor (Verilog)

## 📌 Overview

This project implements a 5-stage pipelined RISC-V (RV32I subset) processor using Verilog.  

The design demonstrates instruction-level parallelism through pipelining and includes core components such as ALU, register file, control unit, and memory modules.

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## 🏗️ Architecture

The processor is divided into the following pipeline stages:

1. **IF (Instruction Fetch)**  

2. **ID (Instruction Decode)**  

3. **EX (Execute)**  

4. **MEM (Memory Access)**  

5. **WB (Write Back)**  

Pipeline registers are used between each stage to ensure proper data flow.

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## ⚙️ Features

- 5-stage pipelined architecture  

- Instruction execution using RV32I base subset  

- Modular RTL design (ALU, Control Unit, Register File, Memory)  

- Simulation-based verification  

- Clean separation of datapath and control logic  

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## 🔍 Current Status

✅ Base pipeline implementation completed  

✅ Instruction execution verified through simulation  

🚧 Hazard handling (data/control hazards) – In Progress  

🚧 Branch prediction – Planned  

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## 🧪 Simulation & Results

- Functional verification performed using testbenches  

- Instruction flow validated across pipeline stages  

- Waveforms confirm correct execution of instructions  

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## 🧱 Modules

- ALU  

- Register File  

- Control Unit  

- Instruction Memory  

- Data Memory  

- Pipeline Registers  

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## 📌 Applications

- Understanding pipelined processor design  

- Instruction-level parallelism concepts  

- Foundation for advanced CPU design (hazards, forwarding, branch prediction)  

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## 🚀 Future Work

- Implement hazard detection and forwarding unit  

- Add branch prediction mechanism  

- Extend instruction support  

- Optimize pipeline performance  

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## 🛠️ Tools Used

- Verilog HDL  

- Xilinx Vivado  

- Simulation Testbenches  

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## 📂 Repository Structure

/source -> RTL design files

/testbench -> Simulation testbenches

/docs -> Diagrams and explanations