https://github.com/cw1997/sdram-controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
https://github.com/cw1997/sdram-controller

hardware hardware-designs sdram sdram-controller systemverilog verilog-project

Last synced: 7 months ago
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SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

• Host: GitHub
• URL: https://github.com/cw1997/sdram-controller
• Owner: cw1997
• License: apache-2.0
• Created: 2021-04-29T13:11:33.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2022-07-01T17:22:12.000Z (over 3 years ago)
• Last Synced: 2025-01-27T07:28:59.679Z (8 months ago)
• Topics: hardware, hardware-designs, sdram, sdram-controller, systemverilog, verilog-project
• Language: HTML
• Homepage:
• Size: 1.5 MB
• Stars: 10
• Watchers: 2
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol