https://github.com/d-iii-s/msim

Light-weight MIPS R4000 and RISC-V system simulator
https://github.com/d-iii-s/msim

hardware-emulation mips32 risc-v

Last synced: about 1 year ago
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Light-weight MIPS R4000 and RISC-V system simulator

• Host: GitHub
• URL: https://github.com/d-iii-s/msim
• Owner: d-iii-s
• License: gpl-2.0
• Created: 2019-09-04T09:38:20.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2025-06-20T14:12:06.000Z (about 1 year ago)
• Last Synced: 2025-06-20T15:27:31.815Z (about 1 year ago)
• Topics: hardware-emulation, mips32, risc-v
• Language: C
• Homepage: https://d3s.mff.cuni.cz/software/msim/
• Size: 3.39 MB
• Stars: 12
• Watchers: 4
• Forks: 6
• Open Issues: 19
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: COPYING
  • Authors: AUTHORS

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README

          
MSIM -- MIPS R4000 and RISC-V system simulator

==============================================

MSIM is a light-weight computer simulator based on MIPS R4000 and RISC-V.

It is used for education and research purposes, mainly to teach

the construction and implementation of operating systems.

MSIM is distributed with source code under the GNU GPL license to make

possible modifications for users and works on most POSIX-compliance

environments (mainly GNU/Linux, Mac OS X, but can be also compiled

in Cygwin or MinGW in Windows).

The user interface is simple terminal-style.

* Project homepage: https://d3s.mff.cuni.cz/software/msim/

* Documentation: https://msim.readthedocs.io/

* Source code: https://github.com/d-iii-s/msim

MSIM provides following features (along others):

* MIPS R4000 CPU

  * full memory management (TLB)

  * multiprocessor support

  * the instruction set is restricted to 32 bits

  * CPU cache is not simulated

* RISC-V RV32IMA CPU

  * A extension

  * M extension

  * Supervisor and User modes

  * multiprocessor support

  * Cache is not simulated

  * Sv32 virtual address translation with TLB simulation

* simple debugging features (including disassembling, register content dump)

* several simple hardware devices

* various hardware-manipulating commands

* widely configurable memory mapping of devices

* script-like start-up configuration file

MSIM does not aim to be a speed-optimized real hardware simulator, but

rather a fully deterministic simulator useful for kernel debugging.

There are several other projects which aim speed-optimized simulation

(e.g. [GXemul](http://gavare.se/gxemul/)), but they are more complex to use.

Compilation and installation

----------------------------

We provide a simple DEB package as part of every

[GitHub release](https://github.com/d-iii-s/msim/releases).

For RPM-based systems we build `msim-git` and `msim` packages at our

[COPR repository](https://copr.fedorainfracloud.org/coprs/d3s/main/)

(`msim` is build with each release while `msim-git` follows the `master`

branch).

Building from sources is possible with standard commands.

    ./configure && make && make test && sudo make install