https://github.com/d0iasm/rvemu-for-book
Reference implementation for the book "Writing a RISC-V Emulator in Rust".
https://github.com/d0iasm/rvemu-for-book
emulator riscv riscv-emulator rust xv6
Last synced: 4 months ago
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Reference implementation for the book "Writing a RISC-V Emulator in Rust".
- Host: GitHub
- URL: https://github.com/d0iasm/rvemu-for-book
- Owner: d0iasm
- License: mit
- Created: 2020-04-10T13:21:37.000Z (about 6 years ago)
- Default Branch: main
- Last Pushed: 2022-08-11T05:20:51.000Z (almost 4 years ago)
- Last Synced: 2025-07-22T20:44:33.778Z (11 months ago)
- Topics: emulator, riscv, riscv-emulator, rust, xv6
- Language: Rust
- Homepage: http://book.rvemu.app/
- Size: 444 KB
- Stars: 385
- Watchers: 22
- Forks: 24
- Open Issues: 3
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# rvemu-for-book
Reference implementation of [the book](https://book.rvemu.app/), *Writing a RISC-V Emulator from Scratch in 10 Steps*. The goal of this code and the book is runnning [xv6](https://github.com/mit-pdos/xv6-riscv) in our emulator.
This is based on original RISC-V emulator [rvemu](https://github.com/d0iasm/rvemu) in Rust.
## How to run xv6
```
$ cd step10 // move to the step10 directory
$ cargo run ./xv6-kernel.bin ./xv6-fs.img
```
## Step to implement a RISC-V emulator
See https://book.rvemu.app/
- Step 1: Setup and Implement Two Instructions
- Step 2: RV64I Base Integer Instruction Set
- Step 3: Control and Status Registers
- Step 4: Privileged Instruction Set
- Step 5: Exceptions
- Step 6: UART (a universal asynchronous receiver-transmitter)
- Step 7: PLIC (a platform-level interrupt controller) and CLINT (a core-local interrupter)
- Step 8: Interrupts
- Step 9: Virtio
- Step 10: Virtual Memory System
Each step has a `diff` file generated by `diff -x target -r step step > diff__`.