https://github.com/deadsy/rvdbg

RISC-V Debugger
https://github.com/deadsy/rvdbg

debugger fe310 gd32v gd32vf103 gigadevice go golang jtag k210 kendryte risc-v riscv sifive

Last synced: 28 days ago
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RISC-V Debugger

• Host: GitHub
• URL: https://github.com/deadsy/rvdbg
• Owner: deadsy
• License: mit
• Created: 2020-01-20T05:44:51.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2023-03-02T17:33:38.000Z (almost 2 years ago)
• Last Synced: 2024-08-03T23:26:45.923Z (4 months ago)
• Topics: debugger, fe310, gd32v, gd32vf103, gigadevice, go, golang, jtag, k210, kendryte, risc-v, riscv, sifive
• Language: Go
• Homepage:
• Size: 892 KB
• Stars: 16
• Watchers: 3
• Forks: 7
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-golang-repositories - rvdbg - V Debugger (Repositories)

README

        
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# rvdbg

RISC-V Debugger

```

$ ./cmd/rvdbg/rvdbg --help

Usage of ./cmd/rvdbg/rvdbg:

  -i string

        debug interface name

  -t string

        target name

debug interfaces:

        daplink     ARM DAPLink   

        jlink       Segger J-Link 

targets:

        gd32v       GD32V Board (GigaDevice GD32VF103VBT6 RISC-V RV32)            

        maixgo      SiPeed MaixGo (Kendryte K210, Dual Core RISC-V RV64)          

        redv        SparkFun RED-V RedBoard (SiFive FE310-G002 RISC-V RV32)       

```