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https://github.com/devbisme/myhdl-resources

A collection of awesome MyHDL tutorials, projects and third-party tools.
https://github.com/devbisme/myhdl-resources

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A collection of awesome MyHDL tutorials, projects and third-party tools.

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README 

        
# MyHDL Resources



> A curated list of tutorials, projects, and third-party tools to be used in conjunction with the

open source [MyHDL](http://myhdl.org/) hardware design language.



*You can add your own stuff to this! Please read the [contribution guidelines](contributing.md) to see how.*



## Table of Contents



- [MyHDL Resources](#myhdl-resources)

  - [Table of Contents](#table-of-contents)

  - [Tutorials](#tutorials)

  - [Projects](#projects)

  - [Third-Party Tools](#third-party-tools)

  - [License](#license)



## Tutorials



- [MyHDL Reference Manual](http://docs.myhdl.org/en/stable/) -

The go-to document for the MyHDL language.



- [Hello World](http://myhdl.org/docs/examples/helloworld.html) -

Shows how a demonstrator design that was originally coded in VHDL can be done in MyHDL.



- [Flip-Flops and Latches](http://myhdl.org/docs/examples/flipflops.html) -

Explains basic MyHDL usage with small, widely-known circuits.



- [Bitonic Sort](http://myhdl.org/docs/examples/bitonic/) -

Presents possibilities for describing hardware structures in MyHDL, focusing on

a classic sorting function.



- [PygMyHDL Tutorials](https://github.com/devbisme/pygmyhdl#getting-started) -

A sequence of Jupyter notebooks that use PygMyHDL (MyHDL + simple wrapper)

to describe, compile, download and run several digital logic circuits on the

low-cost iCEstick FPGA board.



- [MyHDL Cheat Sheet](https://bitbucket.org/nico-dev/myhdl_cheat_sheet/src) -

An abstract for the MyHDL language keywords.



- [modbv Example](https://bitbucket.org/cfelton/examples/src/tip/rrs_modbv/) - 

An example of the use of the modbv type introduced in MyHDL 0.8.



- [LED Strober](https://www.fpgarelated.com/showarticle/25.php) - 

Shows a complete implementation of a circuit that recreates

the strobe effect of the Knightrider Trans Am.



- [Audio Echo](https://www.fpgarelated.com/showarticle/34.php) -

Describes how to produce an echo on a stream of digitized audio samples.

A [companion article](https://www.fpgarelated.com/showarticle/41.php) adds further details

concerning the actual implementation with an AIC23 codec chip.



- [Simple Co-Simulation Example](https://gist.github.com/j-marjanovic/1cd36b9da44280e890b6) -

This code snippet uses three modules to present the absolute minimum for a

co-simulation of Verilog code and MyHDL code.



- [OO Design in MyHDL](https://gist.github.com/josyb/2e43c9ad7ffa772d52dfd66cb660dc4a) -

An example of using object-oriented design principles with MyHDL.



- [FPGA Designs With MyHDL](http://fpga-designs-with-myhdl.readthedocs.io/en/latest/index.html) -

A reimagining of [these VHDL/Verilog designs](http://pythondsp.readthedocs.io/en/latest/pythondsp/toc.html#fpga-designs-with-verilog-and-systemverilog) in MyHDL.



## Projects



- [Johnson Counter](http://myhdl.org/docs/examples/jc2.html) -

Presents the design of a reversible, glitch-free, 4 bit Johnson counter.



- [Stopwatch](http://myhdl.org/docs/examples/stopwatch/) -

Describes the design of a simple stopwatch.



- [Pulse Width Modlator](https://bitbucket.org/cfelton/examples/src/tip/pwm?at=default) -

A simple PWM along with several test setups.



- [Cordic-Based Sine Computer](http://myhdl.org/docs/examples/sinecomp/) -

Presents the design of a sine and cosine computer.



- [Hardware Sorters](https://github.com/devbisme/Hardware-Sorters) -

A [Jupyter](jupyter.org) notebook describing, simulating, and comparing 

two hardware-based circuits for sorting a list of numbers.



- [Exploring Random Number Generators with MyHDL](https://github.com/devbisme/CAT-Board/blob/master/tests/RNG_with_MyHDL.ipynb) -

Illustrates the advantages of using MyHDL and Python in designing and testing a random number generator (RNG).



- [Simple IIR Filter](https://bitbucket.org/cfelton/examples/src/tip/siir/) -

A simple infinite impulse response (IIR) Lowpass Direct Form I Filter.



- [Simple FIR Filter](https://bitbucket.org/cfelton/examples/src/tip/firfilt?at=default) -

A simple finite impulse response (FIR) filter.



- [Recursive FFT](https://bitbucket.org/cfelton/examples/src/tip/rfft/) -

Fast Fourier Transform in MyHDL and translatable to Verilog or VHDL for hardware implementation.

See [this](https://www.dsprelated.com/showcode/16.php) for additional explanation.



- [AIC23b Audio Codec Interface](https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23?at=default) -

An interface for configuring the [AIC23 codec](http://www.ti.com/product/TLV320AIC23B) and sampling/generating audio signals.



- [myhdl_lib](https://github.com/nkavaldj/myhdl_lib) -

A MyHDL library of generic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc. All components are tested with Icarus Verilog simulator.



- [rhea](https://github.com/cfelton/rhea) -

A collection of HDL cores along with a small set of utilities to augment the MyHDL types and functions as well as FPGA build automation tools.



- [KalmanFilter](https://github.com/josyb/KalmanFilter) - 

A simple, low-resource usage Kalman Filter using shared resources.



- [myhdl_simple_uart](https://github.com/andrecp/myhdl_simple_uart) - 

Implements a simple UART in MyHDL and generates the VHDL files. It has been tested in a DE2-115 board.



- [Spiking Neuron](https://github.com/CodeReclaimers/myhdl-experiments/blob/master/izhikevitch/neuron.py) -

Implements a spiking neuron based on the model described in

Izhikevich, E. M., "Simple Model of Spiking Neurons"

IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 6, NOVEMBER 2003.



- [Algol RISCV CPU core](https://github.com/AngelTerrones/Algol) -

A CPU core that implements the RISC-V RV32IM Instruction Set.



- [alt.hdl](https://github.com/cfelton/alt.hdl) -

A collection of complete and partial design examples built using MyHDL, bsv, and chisel.



- [PyMIPS](https://github.com/mgaitan/pymips) -

A formal implementation of a MIPS processor as described in *Computer Organization and Design* by Hennessy/Patterson.



- [RISC-V](https://github.com/jck/riscv) -

A RISC-V implementation and tools.



- [MyBlaze](https://github.com/wware/myblaze) -

a synthesizable clone of the MicroBlaze Soft Processor.



- [Skip-Gram Model for Word Embeddings](https://github.com/gw0/rs-skip-gram-in-myhdl) -

Implementation in MyHDL of a neural network using the skip-gram model for natural language processing.



- [VGA Bouncing Ball](https://github.com/on1arf/myhdl-vga_bounceball) -

A circuit that displays a bouncing ball on a VGA monitor.



- [Whitebox](https://github.com/testaco/whitebox) -

A cross between a smartphone and a software defined radio with the DSP section described using MyHDL.



- [HDL-deflate](https://github.com/tomtor/HDL-deflate) -

Implementation of deflate (de)compress RFC 1950/1951.



- [Kea](https://github.com/SmartAcoustics/Kea) -

Some useful HDL blocks, mainly an AXI Lite register subsystem, along with supporting AXI Lite and Stream interfaces and associated BFMs.



- [Verilog PCIexpressComponents](https://github.com/mongrelgem/Verilog-PCIexpress-Components) -

A collection of PCI express related components including a full MyHDL & Verilog testbench with intelligent bus cosimulation endpoints.



- [myBFSK](https://github.com/Hypotalamus/myBFSK) -

Example of receiver for continuous phase binary frequency shift keying signals with modulation index less then 1.0 written in myHDL.



- [CS3339-MIPS32](https://github.com/grantslape/CS3339-MIPS32) -

This project simulates a MIPS-like 5 stage pipeline through co-simulation between Python and Icarus Verilog. The machine is implemented with a 32-bit architecture through the myHDL library.



- [1pCPU](https://github.com/pcornier/1pCPU) -

A small 8bit CPU written with MyHDL in a Jupyter notebook.



- [jupyosys](https://hackaday.io/project/171216-jupyosys) -

MyHDL extensions to support direct RTL generation and synthesis through yosys 



## Third-Party Tools



- [myhdlpeek](https://github.com/devbisme/myhdlpeek) - 

A Python package that lets you monitor and display signal waveforms from your MyHDL digital design in a Jupyter notebook.



- [PygMyHDL](https://github.com/devbisme/pygmyhdl) - 

A Python package that places a thin-wrapper around MyHDL to make it a bit easier for

beginners to get started.



- [Ovenbird](https://github.com/hgomersall/Ovenbird) - 

A tool for merging the MyHDL workflow with Vivado.



- [MyHDLXilinxUnisimLib](https://bitbucket.org/nico-dev/myhdl_xilinx_unisim_lib/) - 

MyHldXilinxUnisimLib lets you use Xilinx Unisim components within a MyHDL project.



- [Synthia](https://github.com/nturley/synthia) -

A simple IDE that uses MyHDL, yosys, and arachne-pnr to target the ICEStick.



- [pyFDA](https://github.com/chipmuenk/pyFDA) -

A GUI-based tool for analysing and designing discrete time filters.

May be using MyHDL to generate HDL implementations of the filters.



- [Veriutils](https://github.com/hgomersall/Veriutils) -

A collection of utilities for verification of HDL designs created using MyHDL.



- [MyHDL Numeric](https://github.com/jmgc/myhdl-numeric) -

MyHDL-numeric is an enhancement of the MyHDL package which provides support for multiple VHDL entities (MEP110) and fixed-point numbers (MEP111).



- [myhdl2dot](https://github.com/harboleas/myhdl2dot) -

Generates a flowgraph for a MyHDL design using graphviz.



- [VSCode MyHDLTools](https://github.com/rbnprdy/vscode-myhdltools) -

Provides some helpful code generators for using MyHDL for Verilog Cosimulation.



- [HDL playground](https://github.com/hackfin/hdlplayground) -

Jupyter notebook environment for MyHDL/VHDL/Verilog synthesis from the Browser, based on the jupyosys project (Docker container or Google Binder)



## License



[![CC0](http://mirrors.creativecommons.org/presskit/buttons/88x31/svg/cc-zero.svg)](https://creativecommons.org/publicdomain/zero/1.0/)



To the extent possible under law, [Dave Vandenbout]([email protected]) has waived all copyright and related or neighboring rights to this work.