https://github.com/dho-rae/computer-architecture
This repository contains three interconnected projects exploring fundamental computer architecture concepts. The projects focus on assembly language programming, memory management, and CPU simulation. The work was completed as part of a graduate-level Computer Architecture course.
https://github.com/dho-rae/computer-architecture
assembly computer-architecture cpu-simulation memory-management university-project
Last synced: about 2 months ago
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This repository contains three interconnected projects exploring fundamental computer architecture concepts. The projects focus on assembly language programming, memory management, and CPU simulation. The work was completed as part of a graduate-level Computer Architecture course.
- Host: GitHub
- URL: https://github.com/dho-rae/computer-architecture
- Owner: dho-rae
- Created: 2025-03-01T21:45:40.000Z (12 months ago)
- Default Branch: main
- Last Pushed: 2025-03-10T00:24:49.000Z (11 months ago)
- Last Synced: 2025-03-10T01:32:28.884Z (11 months ago)
- Topics: assembly, computer-architecture, cpu-simulation, memory-management, university-project
- Language: Python
- Homepage:
- Size: 11.7 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Computer-Architecture
## Overview
This repository contains coursework projects that focus on understanding the fundamentals of CPU architecture, instruction decoding, caching mechanisms, and pipeline simulation.
## Projects
### 1) Instruction Decoder
- Extracts specific bits from 32-bit MIPS instructions.
- Supports both R-format and I-format instructions.
- Demonstrates instruction decoding using bit masking and shifting.
**Folder**: [`Project-1`](./Project-1)
**Main file**: [`instruction_decoder.py`](./Project-1/instruction_decoder.py)
### 2) Cache Simulator
- Simulates a direct-mapped cache with 16 slots.
- Implements cache read, write, and display operations.
- Uses write-back policy to update main memory.
**Folder**: [`Project-2`](./Project-2)
**Main file**: [`cache.py`](./Project-2/cache.py)
### 3) Pipeline Simulation
- Simulates a five-stage instruction pipeline (IF, ID, EX, MEM, WB).
- Implements register forwarding and hazard detection.
- Displays all pipeline register states at each clock cycle.
**Folder**: [`Project-3`](./Project-3)
**Main file**: [`pipeline_simulator.py`](./Project-3/pipeline_simulator.py)