https://github.com/drom/reqack

🔁 elastic circuit toolchain
https://github.com/drom/reqack

hacktoberfest hardware-description-language hdl verilog

Last synced: 3 months ago
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🔁 elastic circuit toolchain

• Host: GitHub
• URL: https://github.com/drom/reqack
• Owner: drom
• License: mit
• Created: 2016-02-17T06:55:26.000Z (almost 9 years ago)
• Default Branch: trunk
• Last Pushed: 2022-04-22T04:28:27.000Z (almost 3 years ago)
• Last Synced: 2024-10-29T22:51:18.918Z (3 months ago)
• Topics: hacktoberfest, hardware-description-language, hdl, verilog
• Language: JavaScript
• Homepage: https://observablehq.com/collection/@drom/reqack
• Size: 273 KB
• Stars: 29
• Watchers: 4
• Forks: 5
• Open Issues: 24
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-hdl - reqack - elastic circuit toolchain (Meta HDL and Transpilers)

README

        
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[TUTORIAL](https://beta.observablehq.com/@drom/reqack)

# REQuest ⇄ ACKnowledge

JavaScript Tool set to construct, transform and analyze digital circuits based on elastic transactional [protocol](./docs/protocol.md) and Request-Acknowledge handshake.

User describes circuit JavaScript API, add standard components from the library, or create new componets.

Several standard [controllers](./docs/controller.md) provided.

User can transform constructed circuit by changing buffer capacity or performing other correct by construction transformations.

## Usage

The package can be installed from `npm`:

```sh

npm i reqack

```

and imported into your JavaScript code:

```js

const reqack = require('reqack');

```

A **circuit** can be constructed this way:

```js

const g = reqack.circuit('circuit_name');

```

A **node** can be constructed by calling the circuit function. Optional `node_label` string will be used as standard or custom operation or as a root of a signal name.

```js

const node1 = g('node_label');

```

A **edge** can be constructed by calling the node function. Optional argument is an `Object` with two major properties (width, capacity).

```js

const edge1 = node1({width: 32, capacity: 1});

```

One node can be **connected** to another node by calling edge with a destination node.

```js

edge1(node2); // -> edge1

```

Resulted Verilog RTL can be produced by calling

```js

const verilogString = reqack.verilog(g, {});

```

SVG image can be rendered by calling

```js

const svg = reqack.svg(g);

```

## Testing

```sh

npm i

npm test

```

## License

MIT [LICENSE](LICENSE)