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awesome-hdl

Hardware Description Languages
https://github.com/drom/awesome-hdl

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  • HDL doc

    • IEEE Std 1364-2001 - hdl.com/pdfs/verilog_2001_ref_guide.pdf), [SystemVerilog 3.1a](http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf), [Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification](http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)
    • IEEE Std 1076-2000
    • IEEE Std 1666-2011
    • IEEE Std 1364-2001 - hdl.com/pdfs/verilog_2001_ref_guide.pdf), [SystemVerilog 3.1a](http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf), [Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification](http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)
    • IEEE Std 1666-2011

  • HDL simulators and compilers

    • Verilator
    • Icarus Verilog - simulator
    • Yosys - RTL synthesis
    • Lola-2
    • Oberon-2013 - Project Oberon, 2013 Edition, written in [Oberon-07](http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) [License](https://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt)
    • nvc - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
    • GHDL - VHDL compiler and simulator, IEEE 1076-2002, written in ADA
    • essent - firrtl to optimized C++ transpiler
    • treadle - firrtl simulator written in Scala

  • Meta HDL and Transpilers

    • SystemC - an IEEE standard meta-HDL
    • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs
    • jhdl
    • PSHDL
    • shdl - Simple Hardware Description Language
    • Hardcaml
    • Pyrope - Python-like language supporting "fluid pipelines" and "live flow", 2017+
    • ROHD - A framework for hardware description and verification, 2021+
    • CλaSH - A functional hardware description language
    • pipelineDSL - A Haskell DSL for describing hardware pipelines
    • Bluespec - Compiler, simulator, and tools for the Bluespec Hardware Description Language.
    • sv2v - SystemVerilog to Verilog conversion
    • reqack - elastic circuit toolchain
    • hdl-js - Hardware description language (HDL) parser, and Hardware simulator.
    • Julia-Verilog - a Verilog-generation DSL for Julia., 2017
    • Verik
    • HWT - core generator, analysis tools, HDL glue
    • garnet - Grained Reconfigurable Architecture generator based on magma, 2018+
    • migen - Meta HDL, 2011+
    • Amaranth - A refreshed Python toolbox for building complex digital hardware, 2018+
    • MyHDL - Process based HDL, verification framework included, 2004+
    • PyRTL - Meta HDL, simulator suitable for research.
    • PyMTL - Process based HDL, verification framework included, 2014+
    • veriloggen - Python, Verilog centric meta HDL with HLS like features, 2015-?
    • Hdl21 - Analog HDL in Python
    • PyHGL - Meta HDL, three-state event-driven simulation, 2022+
    • RHDL
    • hoodlum - Meta HDL, 2016+
    • kaze - Meta HDL, 2019+
    • Spade - A hardware description language inspired by modern software languages like Rust.
    • SpinalHDL - Meta HDL 2012+
    • Quokka - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)

  • HLS

    • hlslibs - ac_math, ac_dsp, ac_types
    • legup - 2011-2015, LLVM based c->verilog
    • bambu - 2003-?, GCC based c->verilog
    • augh - c->verilog, DSP support
    • abc - ?, A System for Sequential Synthesis and Verification
    • Shang - 2012-2014, LLVM based, c->verilog
    • xronos - 2012, java, simple HLS
    • Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
    • hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
    • hg_lvl_syn - 2010, ILP, Force Directed scheduler
    • DelayGraph - 2016, C#, register assignment algorithms
    • ahaHLS - 2019, An open source high level synthesis (HLS) tool using LLVM
    • combinatorylogic/soc - 2019, An experimental System-on-Chip with a custom compiler toolchain.
    • Quokka - C# to HL RTL translator
    • Vitis - LLVM based, made by Xilinx. [user manual](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf)
    • XLS - 2020, HLS toolchain from Google

  • Other HDL languages

    • TL-Verilog - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools
    • act - asynchronous circuit/compiler tools
    • autopiper
    • Silice - A language for hardcoding algorithms into FPGA hardware

  • Hardware Intermediate Representations

    • CIRCT - 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
    • coreir - 2016-?, LLVM HW compiler## License
    • LLHD - Low Level Hardware Description — A foundation for building hardware design tools
    • SpyDrNet - 2019+, Framework for parsing and manipulating structural netlists in Python
    • VLSIR - IC Interchange Formats, defined in Google Protobuf SDL

  • Visualization and Documentation generators

    • Visual Debug - Custom simulation visualization framework, available within the [Makerchip.com](https://makerchip.com) IDE.
    • d3-wave - Javascript wave graph visualizer for RTL simulations
    • d3-hwschematic - Javascript hierarchical schematic visualizer for HDLs
    • netlistsvg - Javascript schematic visualizer
    • sphinx-hwt - Plugin for sphinx documentation generator which adds schematic into html documentation.

  • Synthesis tools

  • HDL parsers

    • hdlConvertor - Fast (System) Verilog/VHDL parser written as C++ extension for Python
    • pyVHDLParser - VHDL parser written in Python
    • sv-parser - IEEE 1800-2017 System Verilog Parser written in Rust
    • verible - Verible provides a SystemVerilog parser, style-linter, and formatter.
    • slang - SystemVerilog compiler and language service.
    • pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
    • Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

  • Other Simulation tools

    • midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
    • uvvm - A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC.

  • Other Design Automation tools

    • peakrdl - CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT.
    • RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
    • tbengy - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
    • HDLGen - Tool for processing of embedded Perl or Python scripts in Verilog source code.
    • fusesoc - Package manager and a set of build tools for HDL.
    • bender - Dependency management tool for hardware design projects.
    • hbs - A lean dependency management and build system for hardware description projects.

  • PSS : Portable test and Stimulus Standard

Programming Languages
Python 18 C++ 15 Rust 5 Scala 4 Haskell 4 JavaScript 4 Verilog 4 VHDL 2 Ruby 2 Java 1
Categories
Meta HDL and Transpilers 32 HLS 16 PSS : Portable test and Stimulus Standard 14 HDL simulators and compilers 9 Other Design Automation tools 7 HDL parsers 7 HDL doc 5 Visualization and Documentation generators 5 Hardware Intermediate Representations 5 Other HDL languages 4 Other Simulation tools 2 License 2 Synthesis tools 2
Sub Categories
Keywords
verilog 16 fpga 12 vhdl 10 systemverilog 10 compiler 7 parser 6 eda 6 hardware 6 hdl 6 rtl 6 python 5 uvm 4 hardware-description-language 4 asic 4 simulator 4 rust 3 cad 3 linter 2 high-level-synthesis 2 verilog-hdl 2 circuit 2 hls 2 language 2 yosys 2 llvm 2 soc 2 netlist 2 uvm-register-model 2 verification 2 systemverilog-parser 2 scala 2 amba 2 apb 2 axi 2 csr 2 register-descriptions 2 asynchronous-vlsi 1 chp 1 asynchronous-circuits 1 circuit-simulator 1 communicating-hardware-processes 1 pipeline 1 dataflow 1 circuit-analysis 1 dataflow-programming 1 design-automation 1 production-rules 1 prs 1 vlsi 1 intermediate-representation 1