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awesome-hdl

Hardware Description Languages
https://github.com/drom/awesome-hdl

Last synced: 12 days ago
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Hardware Intermediate Representations

  • CIRCT - 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
  • coreir - 2016-?, LLVM HW compiler## License
  • LLHD - Low Level Hardware Description — A foundation for building hardware design tools
  • SpyDrNet - 2019+, Framework for parsing and manipulating structural netlists in Python
  • VLSIR - IC Interchange Formats, defined in Google Protobuf SDL
  • lgraph - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design

HDL doc

HDL Libraries

HDL parsers

  • hdlConvertor - Fast (System) Verilog/VHDL parser written as C++ extension for Python
  • pyVHDLParser - VHDL parser written in Python
  • sv-parser - IEEE 1800-2017 System Verilog Parser written in Rust
  • verible - Verible provides a SystemVerilog parser, style-linter, and formatter.
  • slang - SystemVerilog compiler and language service.
  • pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
  • Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
  • rust_hdl - VHDL parser and language server written in Rust

HDL simulators and compilers

  • Icarus Verilog - simulator
  • Yosys - RTL synthesis
  • Lola-2
  • Oberon-2013 - Project Oberon, 2013 Edition, written in Oberon-07 License
  • nvc - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
  • GHDL - VHDL compiler and simulator, IEEE 1076-2002, written in ADA
  • essent - firrtl to optimized C++ transpiler
  • treadle - firrtl simulator written in Scala
  • ksim - CIRCT IR to optimized C++ transpiler
  • arcilator - Fast and cycle-accurate hardware simulation in CIRCT

HLS

  • hlslibs - ac_math, ac_dsp, ac_types
  • legup - 2011-2015, LLVM based c->verilog
  • bambu - 2003-?, GCC based c->verilog
  • augh - c->verilog, DSP support
  • abc - ?, A System for Sequential Synthesis and Verification
  • Shang - 2012-2014, LLVM based, c->verilog
  • xronos - 2012, java, simple HLS
  • Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
  • hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
  • hg_lvl_syn - 2010, ILP, Force Directed scheduler
  • DelayGraph - 2016, C#, register assignment algorithms
  • ahaHLS - 2019, An open source high level synthesis (HLS) tool using LLVM
  • combinatorylogic/soc - 2019, An experimental System-on-Chip with a custom compiler toolchain.
  • Quokka - C# to HL RTL translator
  • Vitis - LLVM based, made by Xilinx. user manual
  • XLS - 2020, HLS toolchain from Google
  • hector - 2022, An open-source hardware synthesis framework using MLIR
  • bambu - 2003-?, GCC based c->verilog
  • Holoso - 2026+, high-level synthesis of portable Verilog from idiomatic Python for numerical/DSP applications

Meta HDL and Transpilers

  • SystemC - an IEEE standard meta-HDL
  • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs
  • jhdl
  • PSHDL
  • shdl - Simple Hardware Description Language
  • Hardcaml
  • Pyrope - Python-like language supporting "fluid pipelines" and "live flow", 2017+
  • ROHD - A framework for hardware description and verification, 2021+
  • CλaSH - A functional hardware description language
  • pipelineDSL - A Haskell DSL for describing hardware pipelines
  • Bluespec - Compiler, simulator, and tools for the Bluespec Hardware Description Language.
  • sv2v - SystemVerilog to Verilog conversion
  • reqack - elastic circuit toolchain
  • hdl-js - Hardware description language (HDL) parser, and Hardware simulator.
  • Julia-Verilog - a Verilog-generation DSL for Julia., 2017
  • Verik
  • HWT - core generator, analysis tools, HDL glue
  • garnet - Grained Reconfigurable Architecture generator based on magma, 2018+
  • migen - Meta HDL, 2011+
  • Amaranth - A refreshed Python toolbox for building complex digital hardware, 2018+
  • MyHDL - Process based HDL, verification framework included, 2004+
  • PyRTL - Meta HDL, simulator suitable for research.
  • PyMTL - Process based HDL, verification framework included, 2014+
  • veriloggen - Python, Verilog centric meta HDL with HLS like features, 2015-?
  • Hdl21 - Analog HDL in Python
  • PyHGL - Meta HDL, three-state event-driven simulation, 2022+
  • RHDL
  • hoodlum - Meta HDL, 2016+
  • kaze - Meta HDL, 2019+
  • Spade - A hardware description language inspired by modern software languages like Rust.
  • SpinalHDL - Meta HDL 2012+
  • Quokka - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
  • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs
  • PSHDL
  • GateForge - Meta HDL, 2025+
  • Cement - A rule-based Meta HDL inspired by Bluespec, 2024+
  • Veryl - An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog
  • calyx - Intermediate Language (IL) for Hardware Accelerator Generators, 2020+
  • chisel - Meta HDL, 2012+
  • PyXHDL - Python Frontend For VHDL And Verilog, 2023+
  • Filament - Fearless Hardware Design
  • DFHDL - Multi-abstraction Meta HDL, 2021+
  • irtl - a small intermediate representation (IR) builder for RTL. emits FIRRTL or Verilog
  • Filament - Fearless Hardware Design

Other Design Automation tools

  • peakrdl - CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT.
  • RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
  • tbengy - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
  • HDLGen - Tool for processing of embedded Perl or Python scripts in Verilog source code.
  • fusesoc - Package manager and a set of build tools for HDL.
  • bender - Dependency management tool for hardware design projects.
  • hbs - A lean dependency management and build system for hardware description projects.
  • svlint - SystemVerilog linter compliant with IEEE1800-2017. Written in Rust, based on sv-parser.

Other HDL languages

  • TL-Verilog - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools
  • act - asynchronous circuit/compiler tools
  • autopiper
  • Silice - A language for hardcoding algorithms into FPGA hardware
  • AnvilHDL - 2025+, An HDL designed to help avoid common bugs while allowing low-level control through a Rust-like type system
  • ORD - Python-superset HDL for analog and mixed-signal IC design entry, part of the open-source ORDeC design platform
  • TL-Verilog - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

Other Simulation tools

  • midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  • uvvm - A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC.
  • crave - Constrained random stimuli generation for C++ and SystemC (AntMicro's fork of crave)

PSS : Portable test and Stimulus Standard

Synthesis tools

Visualization and Documentation generators

  • Visual Debug - Custom simulation visualization framework, available within the Makerchip.com IDE.
  • d3-wave - Javascript wave graph visualizer for RTL simulations
  • d3-hwschematic - Javascript hierarchical schematic visualizer for HDLs
  • netlistsvg - Javascript schematic visualizer
  • sphinx-hwt - Plugin for sphinx documentation generator which adds schematic into html documentation.