https://github.com/verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://github.com/verilog-to-routing/vtr-verilog-to-routing

cad eda fpga placement routing synthesis verilog vpr vtr

Last synced: about 1 month ago
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Verilog to Routing -- Open Source CAD Flow for FPGA Research

• Host: GitHub
• URL: https://github.com/verilog-to-routing/vtr-verilog-to-routing
• Owner: verilog-to-routing
• License: other
• Created: 2015-06-26T15:24:42.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2024-05-22T15:04:28.000Z (11 months ago)
• Last Synced: 2024-05-22T15:39:39.869Z (11 months ago)
• Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr
• Language: C++
• Homepage: https://verilogtorouting.org
• Size: 291 MB
• Stars: 962
• Watchers: 69
• Forks: 373
• Open Issues: 466
• Metadata Files:
  • Readme: README.developers.md
  • Changelog: CHANGELOG.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE.md
  • Support: SUPPORT.md

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