https://github.com/SystemRDL/PeakRDL

Control and status register code generator toolchain
https://github.com/SystemRDL/PeakRDL

amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog

Last synced: 3 months ago
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Control and status register code generator toolchain

• Host: GitHub
• URL: https://github.com/SystemRDL/PeakRDL
• Owner: SystemRDL
• License: gpl-3.0
• Created: 2020-04-05T18:01:15.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2023-11-08T04:59:33.000Z (12 months ago)
• Last Synced: 2024-07-15T13:53:17.360Z (4 months ago)
• Topics: amba, apb, asic, axi, command-line-tool, csr, eda, fpga, hardware-description-language, register-descriptions, registers, systemrdl-compiler, systemverilog, uvm, uvm-register-model, verilog
• Language: Python
• Homepage: http://peakrdl.readthedocs.io
• Size: 125 KB
• Stars: 78
• Watchers: 12
• Forks: 16
• Open Issues: 5
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-hdl - peakrdl - CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT. (Other Design Automation tools)
• awesome-opensource-hardware - peakrdl

README

        
[![Documentation Status](https://readthedocs.org/projects/peakrdl/badge/?version=latest)](http://peakrdl.readthedocs.io)

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[![Coverage Status](https://coveralls.io/repos/github/SystemRDL/PeakRDL/badge.svg?branch=main)](https://coveralls.io/github/SystemRDL/PeakRDL?branch=main)

[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl.svg)](https://pypi.org/project/peakrdl)

# PeakRDL

PeakRDL is a free and open-source control & status register (CSR) generator

toolchain. This project provides a command-line tool that unifies many aspects

of register automation such as generating Verilog CSR RTL, compiling a

C register abstraction layer, and many more. PeakRDL is centered around the

SystemRDL register description language, but is also capable of working with

other CSR specifications like IP-XACT.

This tool can:

* Process SystemRDL 2.0 register descriptions.

* Generate synthesizable SystemVerilog RTL register blocks.

* Generate a C register abstraction header for software.

* Import & export IP-XACT XML.

* Create rich and dynamic HTML documentation.

* Build a UVM register model abstraction layer.

* ... or extended this tool with your own plugins

## Documentation

See the [PeakRDL Documentation](http://peakrdl.readthedocs.io) for more details.