https://github.com/emsec/hal-benchmarks
Benchmark suite for HAL
https://github.com/emsec/hal-benchmarks
hardware netlist reverse-engineering verilog vhdl
Last synced: 24 days ago
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Benchmark suite for HAL
- Host: GitHub
- URL: https://github.com/emsec/hal-benchmarks
- Owner: emsec
- Created: 2020-07-02T08:23:49.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-11-09T15:05:00.000Z (over 5 years ago)
- Last Synced: 2025-02-28T22:51:03.802Z (about 1 year ago)
- Topics: hardware, netlist, reverse-engineering, verilog, vhdl
- Language: VHDL
- Homepage:
- Size: 9.16 MB
- Stars: 11
- Watchers: 8
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# hal-benchmarks
Collection of various modern open source cores.
## Overview
| Core | Category | LSI_10K | XILINX_UNISIM | Source | Latest Update On |
|-----------|----------|---------|---------------|--------|----------------|
| edge | CPU | 39,607 | 7,237 | [1] | 04/07/2020 |
| ibex | CPU | 12,751 | 6,078 | [2] | 04/14/2020 |
| Open8 | CPU | 1,884 | 1,134 | [3] | 04/07/2020 |
| tiny_aes | Crypto | 144,303 | 7,678 | [4] | 04/07/2020 |
| des | Crypto | 19,217 | 3,770 | [5] | 04/07/2020 |
| BasicRSA | Crypto | 79,787 | 18,672 | [6] | 04/07/2020 |
| sha-3 | Crypto | 15,876 | 6,478 | [7] | 04/07/2020 |
| present | Crypto | 1,393 | 372 | [8] | 04/07/2020 |
| opentitan | SoC | 90,688[1](#f1) | 52,119 | [9] | 04/07/2020 |
1: Some elements (like RAM, Flash...) are implemented as black-boxes
Source:
[1] https://github.com/freecores/edge
[2] https://github.com/lowRISC/ibex
[3] https://opencores.org/projects/open8_urisc
[4] https://opencores.org/projects/tiny_aes
[5] https://opencores.org/projects/des
[6] https://opencores.org/projects/BasicRSA
[7] https://github.com/freecores/sha3
[8] https://opencores.org/projects/present
[9] https://github.com/lowRISC/opentitan