https://github.com/engineersbox/verilogpractice
Practice problems and solutions for verilog
https://github.com/engineersbox/verilogpractice
Last synced: about 1 month ago
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Practice problems and solutions for verilog
- Host: GitHub
- URL: https://github.com/engineersbox/verilogpractice
- Owner: EngineersBox
- Created: 2023-03-04T08:57:09.000Z (almost 3 years ago)
- Default Branch: main
- Last Pushed: 2023-03-05T22:47:12.000Z (almost 3 years ago)
- Last Synced: 2025-02-03T22:46:22.744Z (about 1 year ago)
- Language: Verilog
- Size: 40 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# VerilogPractice
Practice problems and solutions for verilog
## Questions
1. Implement an adder supporting N-bit numbers (parameterised)
2. Create a module representing the following FSM (TODO: FSM diagram)
3. Provide a Verilog module implemented using procedural code with `if-else` for the following table where `S`, `R`, `D` are inputs and `Y` is an output. `X` denotes any value.
| **S** | **R** | **D** | **Y** |
|-------|:-----:|:-----:|-------|
| 1 | 1 | X | X |
| 0 | 1 | X | 0 |
| 1 | 0 | X | 1 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
4. Implement a flip-flop with an active-low async reset
5. Implement an ALU with 3 operations on select:
1. `Y=A+B`
2. `Y=A+1`
3. `Y=max(A, B)`
6. Design and implement a single-port RTL RAM module with parameterised address with, data width and depth.
7. Provide a module for an N-bit shift register
## References
### Problems
### Verilog Explainations