https://github.com/equation-man/risc-vmm
RISC-Virtual Microprocessor Machine
https://github.com/equation-man/risc-vmm
emulation microprocessor risc-v-architecture system-programming virtual-machine
Last synced: 9 months ago
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RISC-Virtual Microprocessor Machine
- Host: GitHub
- URL: https://github.com/equation-man/risc-vmm
- Owner: equation-man
- Created: 2024-12-31T14:55:33.000Z (12 months ago)
- Default Branch: main
- Last Pushed: 2025-01-04T13:21:25.000Z (12 months ago)
- Last Synced: 2025-03-31T08:41:21.354Z (9 months ago)
- Topics: emulation, microprocessor, risc-v-architecture, system-programming, virtual-machine
- Language: Rust
- Homepage:
- Size: 6.84 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# RISC Virtual Microprocessor Machine (RISC-VMM)
This is a RISC-V based CPU emulator software.It assumes a relaxed version of RV32E CPU's instruction set architecture for resource
constrained embedded hardware, emulating how machine code is executed to provide an abstraction of how software controls the CPU
hardware of a computer.
## Short glossary:
#### Instructions
These are primitive CPU commands. They loosely follow RISC-V instruction set architecture (RV32E).
They include moving data, working with memory and primitive arithmetic operations, e.g add, sub, mul, div, lw, sw
#### Machine code
Code that our CPU directly processes. Each instruction is encoded in 32 bits (4 bytes).
#### Opcode
This is a number that maps to an operation. It is important to help determine how the instruction will be executed
#### Registers
Fixed set of temporary storage placeholders for operands in the CPU. Here, we have 16 general purpose registers
which are x0, x1, ..., x15 and other special registers like the program counter(pc) which stores an instruction pointer
which points to the location in RAM where it's going to fetch the next instruction.
Uses load/store memory architecture. Instructions can only operate directly on the data in the registers.
Dedicated instructions, lw and sw are used to load or store data from or to the processor's internal registers.
The processor can only execute instructions on the data stored in the registers as operands, in a fetch-decode-execute cycle.
## Dependencies.
- Rust
- rustc
- Cargo