https://github.com/f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://github.com/f4pga/f4pga-arch-defs

architecture-definitions artix artix7 documentation fpga hdl ice40 kintex7 lattice primitives python sphinx symbiflow synthesis toolchain verilog verilog-simulations verilog-simulator vpr xilinx-fpga

Last synced: about 1 month ago
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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

• Host: GitHub
• URL: https://github.com/f4pga/f4pga-arch-defs
• Owner: f4pga
• License: isc
• Created: 2017-11-16T18:23:49.000Z (over 7 years ago)
• Default Branch: main
• Last Pushed: 2025-04-15T03:39:41.000Z (about 2 months ago)
• Last Synced: 2025-04-15T04:35:13.612Z (about 2 months ago)
• Topics: architecture-definitions, artix, artix7, documentation, fpga, hdl, ice40, kintex7, lattice, primitives, python, sphinx, symbiflow, synthesis, toolchain, verilog, verilog-simulations, verilog-simulator, vpr, xilinx-fpga
• Language: Jupyter Notebook
• Homepage: https://f4pga.org
• Size: 9.52 MB
• Stars: 281
• Watchers: 23
• Forks: 113
• Open Issues: 365
• Metadata Files:
  • Readme: README.md
  • License: COPYING

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• awesome-opensource-hardware - f4pga/f4pga-arch-defs

README

        


  

  

  



# F4PGA Architecture Definitions



  

  

  



**This repository is focused on the development of architecture support in F4PGA. Start with the [![Examples (for Users)](https://img.shields.io/website?longCache=true&style=flat-square&label=F4PGA%20Examples%20for%20Users&up_color=white&up_message=%E2%9E%9A&url=https%3A%2F%2Ff4pga-examples.readthedocs.io%2Fen%2Flatest%2Findex.html&labelColor=231f20)](https://f4pga-examples.readthedocs.io) if you are looking to use the

tools.**

This repo contains documentation of various FPGA architectures, it is currently concentrating on:

* Lattice

  * [iCE40](lattice/ice40)

  * [ECP5](lattice/ecp5)

* AMD/Xilinx

  * [Series 7](xilinx/xc7) (Artix, Kintex and Zynq)

* [QuickLogic](quicklogic)

It includes:

* Black box part definitions

* Verilog To Routing architecture definitions

* Documentation for humans

* Verilog simulations

The aim is to gather useful documentation (both human and machine readable) about the primitives and routing

infrastructure for these architectures.

We hope this enables growth in the open source FPGA tools space.