https://github.com/feritstar/vhdl_tutorials

Fpga examples with Nexys4 DDR board
https://github.com/feritstar/vhdl_tutorials

Last synced: over 1 year ago
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Fpga examples with Nexys4 DDR board

• Host: GitHub
• URL: https://github.com/feritstar/vhdl_tutorials
• Owner: feritstar
• Created: 2021-01-16T12:01:41.000Z (over 5 years ago)
• Default Branch: main
• Last Pushed: 2021-01-16T13:01:59.000Z (over 5 years ago)
• Last Synced: 2025-01-25T09:10:00.009Z (over 1 year ago)
• Language: JavaScript
• Size: 843 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# VHDL_Tutorials

Fpga examples with Nexys4 DDR board

Vivado 2018.3 is used to create these examples.

Hope you enjoyed it!