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https://github.com/francoriba/alu-uart-basys3
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
https://github.com/francoriba/alu-uart-basys3
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog
Last synced: 5 days ago
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UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
- Host: GitHub
- URL: https://github.com/francoriba/alu-uart-basys3
- Owner: francoriba
- Created: 2023-09-27T18:49:53.000Z (about 1 year ago)
- Default Branch: master
- Last Pushed: 2023-11-08T18:31:53.000Z (about 1 year ago)
- Last Synced: 2024-10-11T12:50:54.646Z (about 1 month ago)
- Topics: arquitectura-de-computadores, basys3-fpga, computerarchitecture, fcefyn, hardwaredescription, uart, unc, verilog
- Language: Verilog
- Homepage:
- Size: 537 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# Tp2_UART
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina