https://github.com/furkankayar/deuarc

DEUARC RISC computer design in Quartus II 13.0
https://github.com/furkankayar/deuarc

processor-architecture quartus2 risc

Last synced: 4 months ago
JSON representation

DEUARC RISC computer design in Quartus II 13.0

• Host: GitHub
• URL: https://github.com/furkankayar/deuarc
• Owner: furkankayar
• License: mit
• Created: 2019-04-09T17:40:28.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2020-02-23T14:15:13.000Z (over 5 years ago)
• Last Synced: 2025-01-12T19:26:49.751Z (5 months ago)
• Topics: processor-architecture, quartus2, risc
• Language: VHDL
• Homepage:
• Size: 7.5 MB
• Stars: 2
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
RISC Computer design in Quartus II 13.0