https://github.com/harshalmittal4/24-bit-risc-processor

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA
https://github.com/harshalmittal4/24-bit-risc-processor

isa risc-processor verilog

Last synced: 1 day ago
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Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

• Host: GitHub
• URL: https://github.com/harshalmittal4/24-bit-risc-processor
• Owner: harshalmittal4
• Created: 2018-10-14T23:10:19.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2019-08-25T07:29:09.000Z (over 5 years ago)
• Last Synced: 2024-11-19T09:49:53.928Z (2 months ago)
• Topics: isa, risc-processor, verilog
• Language: Verilog
• Homepage:
• Size: 712 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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README

        
# RISC Processsor 

* Verilog implementation of a 24-bit RISC processor using a self developed ISA. 

## Datapath

![alt text](https://github.com/harshalmittal4/24-bit-MIPS-Processor-Simulation/blob/master/images/Datapath.jpg)

## Instruction Set Architecture (ISA)

![alt text](https://github.com/harshalmittal4/24-bit-MIPS-Processor-Simulation/blob/master/images/ISA.JPG)

## Test Runs


1) LW   r0  r1  00000001                    //load word in memory location 1+$(r0) in r1 

   ADD  r0  r1  r2                          //add  $(r0) and $(r1) and store result in r2

   JUMP  0000000000000011                   //  jump to location 11<<2  i.e  1100 

 

![alt text](https://github.com/harshalmittal4/24-bit-MIPS-Processor-Simulation/blob/master/images/testw1.png)



2)BEQ 101100 00100 00110 00000011



![alt text](https://github.com/harshalmittal4/24-bit-MIPS-Processor-Simulation/blob/master/images/testw2.png)