https://github.com/hdl-util/gray-code

Generate a gray code of arbitrary width in SystemVerilog
https://github.com/hdl-util/gray-code

code coding fpga gray gray-code graycode systemverilog

Last synced: about 4 hours ago
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Generate a gray code of arbitrary width in SystemVerilog

• Host: GitHub
• URL: https://github.com/hdl-util/gray-code
• Owner: hdl-util
• License: other
• Created: 2020-05-23T20:21:40.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-06-27T22:22:32.000Z (over 4 years ago)
• Last Synced: 2024-05-20T17:36:13.624Z (6 months ago)
• Topics: code, coding, fpga, gray, gray-code, graycode, systemverilog
• Language: SystemVerilog
• Homepage: https://purisa.me/blog/arbitrary-width-gray-codes/
• Size: 9.77 KB
• Stars: 2
• Watchers: 3
• Forks: 1
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE-APACHE

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README

        
# Gray code

[![Build Status](https://travis-ci.com/hdl-util/gray-code.svg?branch=master)](https://travis-ci.com/hdl-util/gray-code)

SystemVerilog code for generating a [Gray code](https://en.wikipedia.org/wiki/Gray_code) of arbitrary width.

## Why?

I needed an efficient, easy way to generate gray codes for dual clock FIFOs. It's a pain to manually write out a gray code. Why not let a module do the heavy lifting for you?

## Usage

1. Take files from `src/` and add them to your own project. If you use [hdlmake](https://hdlmake.readthedocs.io/en/master/), you can add this repository itself as a remote module.

1. Other helpful modules are also available in this GitHub organization.

1. Consult the testbench in `test/gray_code_tb.sv` for example usage.

1. Read through the parameter descriptions in `gray_code.sv` and tailor any instantiations to your situation.

1. Please create an issue if you run into a problem or have any questions.

## To-do List

* [ ] [Balanced gray codes](https://github.com/hdl-util/gray-code/issues/1)