https://github.com/hellokenlee/embeddedsystem

Labs for EmbeddedSystem, wirte with verilog
https://github.com/hellokenlee/embeddedsystem

Last synced: 3 months ago
JSON representation

Labs for EmbeddedSystem, wirte with verilog

• Host: GitHub
• URL: https://github.com/hellokenlee/embeddedsystem
• Owner: hellokenlee
• Created: 2014-12-04T07:25:48.000Z (over 11 years ago)
• Default Branch: master
• Last Pushed: 2015-01-08T14:27:57.000Z (over 11 years ago)
• Last Synced: 2026-01-01T01:14:10.668Z (6 months ago)
• Language: Verilog
• Size: 207 KB
• Stars: 0
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
Embedded System Architecture Design

==============

Labs for EmbeddedSystem, wirte with verilog

==============

Lab Environment:

    - Xilinx ISE 12.3 in Ubuntu 14.4LTS

    - Digilent NEXYS3 Board(with Xilinx Spartan -6)

==============

FileSystem:

  -projectName/


  |


  ------------project.v


  |


  ------------projectTest.v


  |


  ------------projectConstrains.ufc


==============

Build Method:

  - in Xilinx ISE 12.3 new a project

  - new a source, choose Verilog Module

  - copy project.v to the new file

  - (optional) new a source, choose Verilog Test Fixture

  - (optional) copy projectTest.v to the new file

  - (optional) choose the TestFile, click ISIM Simulator to run Test

  - new a source, choose Implementation Constraints

  - copy the projectConstrains.ucf to the file

  - click Generate Programming File and wait...

  - if the light turn Green,it success

  - open a terminal, cd to your project dir

  - connect to the NEXYS3 Board

  - run "djtgcfg prog -d Nexys3 -i 0 -f project.bit" to download the programm

  - then you will see the design is onBoard working!