https://github.com/i3abghany/rx32
Fine-grained multithreaded, software-interlocked core in RISC SystemVerilog.
https://github.com/i3abghany/rx32
assembler fpga microarchitecture pipeline system-verilog
Last synced: 4 months ago
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Fine-grained multithreaded, software-interlocked core in RISC SystemVerilog.
- Host: GitHub
- URL: https://github.com/i3abghany/rx32
- Owner: i3abghany
- Created: 2020-05-04T19:02:45.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2025-06-04T17:25:19.000Z (4 months ago)
- Last Synced: 2025-06-04T22:41:39.838Z (4 months ago)
- Topics: assembler, fpga, microarchitecture, pipeline, system-verilog
- Language: C
- Homepage:
- Size: 532 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Rx32-FGMT
A fine-grained multithreaded, five-stage pipelined microarchitecture
implementation. It deals with hazards by filling the pipeline with instructions
from 5 separate programs.