https://github.com/isaaczhang4/mips-cpu

Verilog Implementation of a Pipelined MIPS Single Cycle CPU
https://github.com/isaaczhang4/mips-cpu

cpu-simulator hardware hardware-simulation mips-architecture verilog

Last synced: 2 months ago
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Verilog Implementation of a Pipelined MIPS Single Cycle CPU

• Host: GitHub
• URL: https://github.com/isaaczhang4/mips-cpu
• Owner: IsaacZhang4
• License: mit
• Created: 2025-02-01T20:33:35.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2025-02-01T20:38:43.000Z (about 1 year ago)
• Last Synced: 2025-02-10T19:39:16.969Z (about 1 year ago)
• Topics: cpu-simulator, hardware, hardware-simulation, mips-architecture, verilog
• Language: Verilog
• Homepage:
• Size: 11.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# MIPS-CPU

Verilog Implementation of a Pipelined MIPS Single Cycle CPU

Includes data forwarding feature which heavily optimizes the basic MIPS CPU