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https://github.com/isaaczhang4/mips-cpu
Verilog Implementation of a Pipelined MIPS Single Cycle CPU
https://github.com/isaaczhang4/mips-cpu
cpu-simulator hardware hardware-simulation mips-architecture verilog
Last synced: about 9 hours ago
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Verilog Implementation of a Pipelined MIPS Single Cycle CPU
- Host: GitHub
- URL: https://github.com/isaaczhang4/mips-cpu
- Owner: IsaacZhang4
- License: mit
- Created: 2025-02-01T20:33:35.000Z (9 days ago)
- Default Branch: main
- Last Pushed: 2025-02-01T20:38:43.000Z (9 days ago)
- Last Synced: 2025-02-01T21:29:00.176Z (9 days ago)
- Topics: cpu-simulator, hardware, hardware-simulation, mips-architecture, verilog
- Language: Verilog
- Homepage:
- Size: 0 Bytes
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# MIPS-CPU
Verilog Implementation of a Pipelined MIPS Single Cycle CPU
Includes data forwarding feature which heavily optimizes the basic MIPS CPU