https://github.com/itsuren/computerarchitecture

🏛️ [RUSHED🏃‍♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.
https://github.com/itsuren/computerarchitecture

vhdl-code vhdl-coursework

Last synced: about 2 months ago
JSON representation

🏛️ [RUSHED🏃‍♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.

• Host: GitHub
• URL: https://github.com/itsuren/computerarchitecture
• Owner: ITSUREN
• License: mit
• Created: 2024-04-23T04:51:56.000Z (9 months ago)
• Default Branch: main
• Last Pushed: 2024-06-14T15:17:31.000Z (7 months ago)
• Last Synced: 2024-10-09T18:03:47.177Z (3 months ago)
• Topics: vhdl-code, vhdl-coursework
• Language: VHDL
• Homepage:
• Size: 707 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        


	


	

	Computer Architecture

	

 



	

		

	

		



 

A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for classroom material.


 

### ❤️ Contributors

Thanks for making this project possible:

|  | Saugat Tamang |

|----------------|----------------|

 

### 📜 License

Get Closest is released under the [MIT license](./LICENSE), which grants the following permissions:

- Commercial use

- Distribution

- Modification

- Private use